What Is a 32 Layer PCB Copy and Why Is It Different?
A 32 layer PCB copy is the full reverse engineering of a printed circuit board containing 32 copper layers—recovering Gerber data, the complete stackup, drill files, and a bill of materials from a physical sample. At this layer count, the board almost certainly uses sequential lamination with multiple sub-stack press cycles, buried and stacked microvias, and tightly controlled impedance on dozens of differential pairs. These characteristics make a 32 layer PCB copy fundamentally harder than anything below 20 layers, and the margin for error on each layer drops to near zero.
Why 32-Layer Boards Exist—and Who Needs Them Copied
Boards at this density appear in high-performance computing (server blades, GPU accelerator cards), telecom backbone switches, advanced radar/EW modules, and medical imaging processors. The original design files are frequently lost during acquisitions, end-of-life declarations, or supplier exits. Engineers come to us when:
- The OEM no longer supports the product and no Gerber data survives.
- A legacy system must remain in production but the original fab house has closed.
- A redesign requires understanding the existing stackup and routing before modifying it.
- Second-source qualification demands an independent data package for comparison.
How We Perform a 32 Layer PCB Copy
1. Incoming Inspection and Layer-Count Verification
We cross-section the board edge or a sacrificial coupon under a metallurgical microscope at 200–500× to confirm the exact layer count, dielectric thicknesses (typically 3.0–4.5 mil prepreg, 1.0–2.0 mil core in HDI sub-stacks), and copper weights (commonly ½ oz signal, 1 oz plane). This step catches mislabeled boards—some “32-layer” assemblies are actually 30 or 34 layers with asymmetric builds.
2. Component Removal and BOM Extraction
Every component is cataloged—package, value, manufacturer part number, and orientation. On a 32-layer design, BGA pitch can be as fine as 0.4 mm with 2,500+ balls, and passives often sit in 01005 packages. We photograph placement before desoldering to preserve polarity and rotation data.
3. Layer-by-Layer Imaging
Each copper layer is exposed through controlled chemical or mechanical delayering. We capture high-resolution optical scans (≥2400 DPI, typically 4800 DPI on fine-pitch areas) of every layer. At 32 layers, registration drift between sub-stacks is a real risk; we use fiducial alignment marks and via centroid matching to maintain ±0.5 mil (12.7 µm) layer-to-layer accuracy.
4. Via Structure Mapping
A 32-layer board will have through-hole vias, blind vias (typically L1–L4 or L29–L32), buried vias spanning interior sub-stacks, and possibly stacked or staggered microvias. We map every via type, its start/end layers, and drill diameter (often 4 mil laser-drilled microvias, 8–12 mil mechanical vias). This via map is critical—getting it wrong means the board cannot be fabricated.
5. Stackup Reconstruction and Impedance Modeling
Using the cross-section measurements, we rebuild the full stackup in a 2D field solver (e.g., Polar Si9000). Target impedances are back-calculated from trace geometry: a 4.0 mil trace on 3.5 mil prepreg (Dk ≈ 3.9 for Megtron 6) yields roughly 50 Ω single-ended; differential pairs at 4/4/8 mil trace/space/pair spacing target 100 Ω. We document every layer’s impedance class so the fabricator can match materials.
6. Gerber Output, DRC, and Verification
Vectorized artwork is exported as Gerber X2 (or RS-274X) with an Excellon drill file set. We run full DRC against IPC-2221B Class 2 or Class 3 rules, depending on the application. The final data package includes a fabrication drawing with the stackup table, impedance requirements, material callouts, and via drill chart.
Typical Stackup Profile for a 32-Layer Board
| Layer | Function | Copper Weight | Dielectric Below (mil) |
|---|---|---|---|
| L1 | Signal (microstrip) | ½ oz | 3.5 prepreg |
| L2 | Ground plane | 1 oz | 3.0 core |
| L3 | Signal (stripline) | ½ oz | 3.5 prepreg |
| L4 | Power plane | 1 oz | 4.0 core |
| L5–L28 | Alternating signal/plane | ½–1 oz | 3.0–4.5 |
| L29 | Power plane | 1 oz | 4.0 core |
| L30 | Signal (stripline) | ½ oz | 3.5 prepreg |
| L31 | Ground plane | 1 oz | 3.0 core |
| L32 | Signal (microstrip) | ½ oz | — |
Actual stackups vary by material system. Megtron 6, IS415, and Tachyon 100G are common at this layer count. We identify the material family from Dk/Df measurements and resin color during cross-sectioning.
Cost and Lead Time for 32 Layer PCB Copy
| Factor | Typical Range |
|---|---|
| Reverse engineering (Gerber + stackup) | $6,000–$18,000 |
| BOM extraction | $800–$2,500 |
| Schematic recovery (optional) | $4,000–$12,000 |
| Lead time (RE only) | 15–25 working days |
| Prototype fabrication (if ordered) | 20–30 working days additional |
| Samples required | Minimum 2 (1 sacrificial) |
Price depends on board area, BGA count, via complexity, and whether schematic recovery is included. Boards larger than 400 × 300 mm or with more than 8 BGA sites above 1,500 balls each push toward the upper range. We provide a binding quote after a free feasibility review of photographs and X-ray images.
What Makes a 32 Layer PCB Copy Harder Than 16 or 20 Layers?
Every additional layer pair compounds three problems:
- Delayering precision. Removing copper and dielectric 32 times without damaging the next layer requires tighter process control. Over-etch on layer 14 can destroy traces on layer 15.
- Via complexity. A 16-layer HDI board copy might have 3 via span types. A 32 layer PCB copy can involve 6–8 distinct span types, including buried vias that connect only interior sub-stacks (e.g., L8–L12). Missing one span type means the fabricated board has open circuits.
- Material sensitivity. At 32 layers, total board thickness can reach 4.5–6.0 mm. Aspect ratios for through-hole vias (board thickness ÷ drill diameter) hit 15:1 or higher, pushing fabrication limits. Our Gerber output must specify drill sizes and plating requirements that the fab can actually achieve.
For comparison, a 20-layer multilayer reverse engineering project typically involves 3–4 via types and completes in 12–18 days. The jump from 20 to 32 layers is not linear—it roughly doubles the imaging and verification effort.
Failure Modes We Guard Against
Registration Error Accumulation
After 16+ delayering steps, cumulative registration drift can exceed 1 mil if fiducials are not re-referenced at each layer. We re-anchor to at least 4 fiducial points per layer and cross-check via centroids against the master drill file.
Misidentified Plane Splits
Power planes on 32-layer boards often carry 4–6 different voltage rails on a single layer with thin isolation gaps (5–8 mil). A low-resolution scan can miss a split, shorting two rails in the output Gerber. We scan plane layers at 4800 DPI minimum and verify every split against the BOM’s voltage requirements.
Impedance Mismatch After Fabrication
If the stackup reconstruction uses the wrong Dk value (e.g., assuming FR-4 at 4.2 when the board is Megtron 6 at 3.7), impedance on differential pairs can be off by 8–12 Ω. On 10 Gbps+ SerDes links common in 32-layer server boards, that mismatch causes eye diagram failures. We measure Dk directly from the cross-section and validate against the material datasheet.
Deliverable Package
- Gerber X2 files for all 32 copper layers, solder mask (top/bottom), silkscreen (top/bottom), paste mask (top/bottom).
- Excellon drill files—separate files per via span type (through, blind, buried).
- Fabrication drawing with full stackup table, impedance targets, material callout, and drill chart.
- BOM in Excel/CSV with MPN, package, value, designator, and placement coordinates.
- Pick-and-place centroid file (optional).
- Schematic in Altium/OrCAD/KiCad format (if ordered).
How This Compares to Other Layer Counts
If your board is simpler, our process scales down accordingly. A 10-layer board with multiple signal pairs typically costs $2,000–$5,000 and finishes in 8–12 days. Even a four-layer board with power and ground planes benefits from proper stackup recovery, though the effort is far smaller. At the high end, 24-layer backplane and server board copy projects share many of the same HDI challenges as 32 layer PCB copy work but with fewer sub-stack press cycles.
Frequently Asked Questions
How many board samples do you need for a 32 layer PCB copy?
We require a minimum of two samples. One is sacrificially delayered for imaging. The second serves as a reference for component placement verification and electrical spot-checks. If the board is rare, we can sometimes work with one sample plus detailed X-ray images, but accuracy may be reduced on buried via mapping.
Can you match the original high-speed material (Megtron 6, IS415) in the copy?
Yes. We identify the material family during cross-sectioning by measuring Dk, Df, resin color, and glass weave style. The fabrication drawing specifies the material by name or equivalent, and we work with fabs that stock these laminates. Substituting generic FR-4 on a 32-layer 10 Gbps+ design would cause signal integrity failures.
What if some layers are too damaged to image clearly?
Localized damage (corrosion, burn marks) on one or two layers can often be reconstructed from adjacent reference planes and netlist continuity checks. If more than 3 layers are severely compromised, we flag this during feasibility review before quoting. We will not deliver data we cannot verify.
Is the output data fabrication-ready or does it need further engineering?
Our Gerber and drill files are fabrication-ready and DRC-verified. We include a complete fab drawing. Most customers send the package directly to their preferred PCB fabricator without modification. If your fab has specific format requirements (ODB++, IPC-2581), we can convert.
Start Your 32 Layer PCB Copy Project
Send us clear photos of both sides of the board, approximate dimensions, and any X-ray images you have. Our engineers will confirm the layer count, identify potential complications, and return a fixed-price quote within two business days. Explore our full reverse engineering service overview or request a feasibility review now.
[pcb_cta type=”quote”]
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote