6 Layer PCB Copy: Stackup Recovery & Impedance Guide

Why a 6 Layer PCB Copy Is Harder Than It Looks

A 6 layer PCB copy sits in a deceptive middle ground. The board is complex enough to carry high-speed differential pairs, multiple power rails, and dense BGA breakouts, yet simple enough that engineers sometimes underestimate the reverse-engineering effort. In practice, every 6 layer PCB copy project fails or succeeds based on one decision: how accurately you reconstruct the signal-plane assignment and the impedance environment that surrounds every critical trace.

Unlike a four-layer board—where the stackup is almost always Signal–Ground–Power–Signal—a six-layer design can follow at least three common arrangements, each with different impedance profiles. Getting the assignment wrong by even one layer means every controlled-impedance trace in the clone will be off-target, and no amount of post-fabrication tuning can fix that.

If you are working on a project with more layers, our overview of how layer count changes method, price, and risk provides the broader context you need before diving into six-layer specifics.

Common 6 Layer PCB Copy Stackup Arrangements

Before you power up the cross-section microscope, it helps to know what you are likely to find. The three dominant configurations for a six-layer board are listed below.

Option A is the workhorse: two outer signal layers referenced to adjacent ground or power planes, plus an inner signal layer sandwiched between planes. Option B moves the inner signal layer between two ground planes, creating a symmetric stripline ideal for high-speed differential pairs. Option C sacrifices a signal layer to carry multiple supply voltages—common in industrial power converters and motor drives.

How to Decide Which Stackup Your Donor Board Uses

The fastest initial clue comes from component placement. If the board carries DDR memory, SERDES transceivers, or high-speed connectors, Option B is the most likely candidate because designers prefer symmetric stripline for length-matched differential pairs. If you see large power MOSFETs, multiple voltage regulators, and wide copper pours on the outer layers, Option C is probable. Option A covers the majority of general-purpose designs—consumer electronics, IoT gateways, and mid-range industrial controllers.

Identifying which arrangement your donor board uses is the first milestone in any 6 layer PCB copy project. Use the interactive tool below to compare your measurements against known stackup templates.

Step-by-Step: Recovering the Stackup

1. Non-Destructive Inspection

Start with what you can see. Photograph both outer layers at high resolution—at least 2400 DPI for boards with 4 mil trace/space rules. Catalog every via: through-hole, blind, or buried. On a six-layer board, blind vias typically span L1–L2 or L5–L6, while buried vias connect L2–L5 or L3–L4. If you spot blind and buried via structures that cannot be seen from the surface, mark them now; they constrain the lamination sequence and therefore the stackup.

Also note the overall board thickness with a micrometer. A standard 62 mil (1.6 mm) six-layer board has roughly 4–5 mil dielectric between adjacent layers. A thinner board—say 40 mil—signals tighter dielectric spacing and possibly thinner copper, both of which change impedance calculations significantly.

2. Cross-Sectioning

Select a sacrificial area—ideally near a board edge with through-hole vias that pass all six layers. A metallographic cross-section reveals:

• Copper thickness on each layer (typically 1 oz outer, 0.5 oz inner, but not always).
• Dielectric thickness between adjacent copper layers—the single most important impedance variable.
• Prepreg vs. core identification. Cores are cured laminates with copper on both sides; prepregs are partially cured sheets that bond cores together during lamination.
• Dielectric material type. Standard FR-4 (Dk ≈ 4.2–4.5) looks different under polarized light from high-speed laminates like Megtron 6 (Dk ≈ 3.6). If you suspect a specialty material, consult our guide on the high-frequency PCB copy process for identification techniques.

3. Recording Measurements

Measure at least three cross-section locations to average out fabrication tolerances. Document each value in a table like this:

This symmetric pattern is typical of Option A or Option B stackups. An asymmetric measurement usually signals a non-standard design or a mixed-material build. When the numbers don’t match any common template, you may be dealing with a design that was originally optimized for a specific fabricator’s proprietary stackup—document everything and contact the fab house for the closest available match.

Signal-Plane Assignment: Getting It Right

Once you have the physical stackup, assign each layer’s function. The rules are straightforward but unforgiving:

1. Planes are easy to identify. A layer that is almost entirely copper fill with only clearance holes around vias is a plane. Determine whether it connects to ground or a power rail by probing via pads with a multimeter on the donor board.
2. Inner signal layers carry routed traces. After delayering, photograph L3 and L4 (or whichever layers are inner signal). The trace widths here are your stripline geometry.
3. Reference plane adjacency matters. A signal trace on L3 referenced to a ground plane on L2 and a power plane on L4 forms an asymmetric stripline. Its impedance differs from a symmetric stripline referenced to ground on both sides. Record which planes border each signal layer.

For projects that scale beyond six layers, the same principles apply with greater complexity. Our walkthrough of eight-layer stackup reconstruction and dielectric recovery shows how the method extends when additional plane pairs enter the picture.

Impedance Preservation: The Core Challenge of 6 Layer PCB Copy

Controlled impedance is not a single number—it is a system of trace width, copper thickness, dielectric thickness, and dielectric constant working together. Change any one variable and the impedance shifts. During a 6 layer PCB copy, you must preserve the system, not just the trace geometry.

Microstrip Traces (L1 and L6)

Outer-layer traces sit on top of a dielectric with a reference plane below. The key variables are:

• Trace width (W)
• Copper thickness (T)
• Dielectric height to the reference plane (H)
• Solder mask thickness and Dk (often overlooked—solder mask lowers effective Dk by 0.2–0.5)

A typical 50 Ω single-ended microstrip on standard FR-4 with H = 4.5 mil and 1 oz copper requires a trace width around 7.5–8.0 mil. If your fabricator uses a different prepreg thickness—say 5.0 mil instead of 4.5 mil—the trace must widen to roughly 8.8 mil to maintain 50 Ω.

Worked Example: Recalculating Trace Width for a New Fabricator

Suppose the donor board’s cross-section shows a 7.8 mil trace on L1 with H = 4.5 mil, T = 1.4 mil (1 oz), and Dk = 4.25. You send the Gerber files to a fabricator whose closest available prepreg gives H = 5.2 mil and Dk = 4.10. Using a 2D field solver:

1. Original impedance: Z₀ ≈ 50.2 Ω (matches the 50 Ω target).
2. New impedance with the same 7.8 mil trace but H = 5.2 mil, Dk = 4.10: Z₀ ≈ 55.8 Ω—over 10 % high.
3. Adjusted trace width to restore 50 Ω: approximately 9.3 mil.

This 1.5 mil increase in trace width may seem small, but on a dense BGA breakout it can violate clearance rules. Always run the impedance solver before committing to a fabricator’s stackup offering.

Stripline Traces (Inner Signal Layers)

Inner traces are sandwiched between two planes. Symmetric stripline (equal dielectric on both sides) is the easiest to control. Asymmetric stripline (unequal dielectric) requires careful modeling because the impedance depends on both dielectric thicknesses and both Dk values.

For designs where impedance accuracy is mission-critical—such as DDR4 memory buses or SERDES lanes—refer to our dedicated resource on impedance-controlled PCB copy when the original spec is unavailable.

Differential Pairs

Most six-layer boards carry at least one differential pair: USB, Ethernet, LVDS, or HDMI. Differential impedance depends on the same variables as single-ended impedance plus the gap between the two traces. During copy, measure both the trace width and the gap on every differential pair. A 1 mil change in gap can shift differential impedance by 5–8 Ω.

For example, a USB 2.0 pair targeting 90 Ω differential on L5 (stripline, symmetric, H₁ = H₂ = 8 mil, Dk = 4.35) might use 5 mil traces with a 6 mil gap. If your measurement shows 5 mil traces with a 7.5 mil gap, the differential impedance rises to approximately 96 Ω—still within the USB ±15 % tolerance, but dangerously close to the limit if the fabricator’s dielectric is also slightly off.

Delayering a Six-Layer Board

Delayering is the process of removing copper and dielectric layers one at a time to photograph each layer’s artwork. For a six-layer board, the typical sequence is:

1. Photograph L1 (top) and L6 (bottom) before any processing.
2. Chemically etch away L1 copper.
3. Mechanically or chemically remove the L1–L2 dielectric to expose L2.
4. Photograph L2.
5. Repeat for L3, L4, and L5.

Each photograph is then vectorized into Gerber data. Registration accuracy between layers must be within ±0.5 mil for BGA-class designs. This is where six-layer projects diverge from simpler boards: with three dielectric removal steps instead of one, cumulative registration error grows. Use fiducial marks or through-hole via centers as alignment anchors on every layer.

Handling Filled and Capped Vias

Many six-layer boards use vias filled with epoxy and capped with copper to allow component pads directly on top of vias (via-in-pad). During delayering, the epoxy fill can obscure the via barrel and make it harder to identify the via span. Use back-lighting or X-ray imaging before delayering to map filled vias. This step prevents misidentifying a blind via as a through-hole via—a mistake that would corrupt the drill file in your 6 layer PCB copy output.

When the board also features HDI construction with microvias, the delayering complexity increases further. Our guide to HDI board copy projects involving microvias and build-up layers explains the additional precautions required.

Fabrication Notes That Protect Your Clone

Once you have Gerber files, a drill file, and a stackup drawing, the fabrication package must communicate the impedance intent clearly. Include the following in your fab notes:

• Target impedances for each controlled-impedance class (e.g., 50 Ω single-ended microstrip, 100 Ω differential stripline).
• Dielectric material and Dk at the operating frequency. Specify the prepreg style (e.g., 2116, 1080, 106) and the resin content percentage if known.
• Copper weight per layer. Inner layers are often 0.5 oz; outer layers 1 oz. State this explicitly.
• Impedance tolerance. Industry standard is ±10 %, but high-speed designs may need ±7 %.
• Test coupon requirement. Ask the fabricator to include TDR test coupons on the panel and to report measured impedance values.
• Stackup drawing with layer functions. Label each layer as Signal, Ground, or Power, and indicate the reference plane for every signal layer.

Common Pitfalls in 6 Layer PCB Copy Projects

When Six Layers Are Not Enough—or Too Many

Sometimes the donor board is six layers, but the redesign context has changed. If you are consolidating functions onto fewer layers—or if the original design was over-specified—consider whether a four-layer clone with thicker dielectrics could meet the same impedance targets at lower cost.

Conversely, if you are copying a six-layer board that pushes every layer to its routing limit, a move to ten layers may actually reduce risk. Our discussion of ten-layer boards where delayering accuracy dominates cost explains the trade-offs involved in scaling up.

Verification After Fabrication

A successful 6 layer PCB copy does not end at the fab house. Post-fabrication verification should include:

• TDR measurement on test coupons and, if possible, on critical nets of the assembled board.
• X-ray inspection of blind and buried vias to confirm correct span and fill quality.
• Functional testing against the donor board’s known behavior—bit error rates, eye diagrams, or power rail ripple, depending on the application.
• Cross-section of one production panel to confirm that the fabricator hit the specified dielectric thicknesses and copper weights.
• Automated optical inspection (AOI) to catch solder defects, missing components, and tombstoned passives before functional test.

A 6 layer PCB copy is only as good as the stackup it rides on. Get the signal-plane assignment and dielectric measurements right, and the rest of the project follows. Get them wrong, and no amount of trace-width adjustment will save you.

Frequently Asked Questions

How long does a typical 6 layer PCB copy project take?

A straightforward 6 layer PCB copy—with standard FR-4, no blind or buried vias, and moderate component density—typically takes 5 to 8 working days from donor board receipt to final Gerber output. Projects with HDI features, high-speed laminates, or dense BGA arrays can extend to 12–15 days because cross-sectioning, impedance modeling, and delayering each require additional iterations. Fabrication lead time (usually 5–10 days for a six-layer prototype) is separate.

Can I perform a 6 layer PCB copy without destroying the donor board?

Partially. Non-destructive methods—high-resolution photography of outer layers, X-ray imaging of inner layers and vias, and TDR probing of impedance—can recover a significant portion of the design data. However, accurately measuring dielectric thickness and identifying the exact prepreg or core material almost always requires at least one destructive cross-section. The best practice is to sacrifice a small area near the board edge while keeping the rest of the board functional for reference testing.

What is the cost difference between copying a 4-layer and a 6-layer board?

Expect a 6 layer PCB copy to cost 40–70 % more than a four-layer copy of similar board dimensions. The premium comes from three sources: additional delayering steps (two extra layers to expose and photograph), more complex impedance modeling (inner stripline layers require precise dielectric data), and longer cross-section analysis. Fabrication cost for the cloned board is also higher—roughly 30–50 % more than a four-layer board of the same size, depending on the fabricator.

Do I need to match the exact same dielectric material as the original board?

Not always, but you must match the electrical properties—primarily Dk and Df (dissipation factor) at the operating frequency. If the original board uses a standard FR-4 with Dk ≈ 4.3, any equivalent FR-4 from a different supplier will work as long as the fabricator adjusts trace widths based on their specific prepreg and core thicknesses. For high-frequency designs above 3 GHz, material substitution is riskier because Dk variation between suppliers can exceed 5 %, which directly impacts impedance and signal loss.

Whether your next project involves six layers or extends into higher-density territory, the methodology remains the same: measure, model, verify, and document every variable that influences signal and power integrity.

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