Aerospace PCB reverse engineering is priced off four things: layer count, component density, whether you need firmware recovered, and how much documentation you need on the back end. A two-layer analog signal-conditioning card is a short job. A twelve-layer avionics processor board with BGAs, buried vias, and a locked MCU is a multi-week project. Lead time follows the same curve. Below is how we scope it, what we need from you, and where the honest limits sit.
Why aerospace boards cost more than the same board from another industry
The copper is not the hard part. The paperwork expectations are.
An industrial motor drive card gets reverse engineered, prototyped, tested, and shipped. An aerospace board usually has to come with a traceable material declaration, a stackup that can be defended in a review, and an acceptability spec someone in quality will actually check against. That means we do not just recover the artwork — we characterize it. Dielectric thicknesses get measured on a cross-section rather than guessed. Copper weight gets confirmed. Impedance targets on controlled-impedance nets get calculated back from the measured geometry and sanity-checked against what the original designer plausibly intended.
That extra characterization work is typically 20 to 40 percent of the engineering hours on an aerospace job compared with the same physical board destined for a commercial product. It is also the part that makes the deliverable useful to you, because a Gerber set with no verified stackup is not something you can fabricate to IPC-6012 Class 3 with any confidence.
The Class 3 factor
Most aerospace and avionics hardware is built to IPC-6012 Class 3, with visual acceptance per IPC-A-600 Class 3. That changes the reverse engineering output in concrete ways: annular ring requirements are tighter, so we cannot round pad geometry to something convenient; plating and hole wall expectations are stricter, so the drill and finished-hole callouts need real numbers, not nominal ones. If your recovered files will feed a Class 3 build, tell us up front. It affects how we dimension things, and it is cheaper to do it right the first time than to re-derive it after a fabricator rejects the package.
What actually drives the number on your quote
We quote engineering hours, not board area. These are the variables that move the hours, roughly in order of impact:
- Layer count. Inner layers have to be imaged individually after controlled delamination. Going from 4 to 8 layers roughly doubles that phase; going to 16 or 20 more than doubles it again, because thin cores are fragile and some need to be imaged in sections and stitched.
- Via structure. Through-hole only is straightforward. Blind and buried vias, or an HDI stack with microvias, require X-ray and careful layer-by-layer correlation to get the connectivity right. This is one of the biggest single cost jumps on modern avionics boards.
- Component count and package type. Fine-pitch BGAs, QFNs with no visible leads, and bottom-terminated passives all need X-ray or removal to confirm pinout and value. A 400-part board with three BGAs takes far longer than a 400-part board of SOICs.
- Unmarked and remarked parts. Aerospace boards are full of military-grade parts with house numbers instead of manufacturer part numbers. Cross-referencing a “CAGE code + drawing number” marking to an actual orderable component is research time, and sometimes the answer is “this was a custom screen and no drop-in equivalent exists.”
- Depth of deliverable. Gerbers and a BOM is the cheapest tier. Add a full hierarchical schematic and you add significant hours, because every net has to be traced, named, and grouped into functional blocks a human can read. Add analysis of the analog design intent and it goes up again.
- Firmware. If a programmed MCU, FPGA, or CPLD has to come back functional, that is a separate workstream with its own feasibility question.
- Conformal coating and potting. Almost every flight board is coated. Parylene and silicone come off with reasonable effort. Filled epoxy potting is slow and sometimes destroys the sample.
If you want to see how these same drivers scale across board classes outside aerospace, our general breakdown of PCB reverse engineering cost and lead time covers the baseline we build on top of.
Realistic lead times by board class
These are engineering-phase ranges for a single sample, from the day the board lands in the lab to the day we hand over files. They assume one good sample, coating that comes off cleanly, and no firmware work. Add fabrication and assembly time on top if you want physical boards.
| Board class | Typical example | Engineering lead time | What usually slows it down |
|---|---|---|---|
| 2 layer, low density | Sensor interface, LED annunciator card | A few days | Almost nothing. Unmarked passives at worst. |
| 4 layer, moderate density | Power distribution, discrete I/O card | Around one to two weeks | Plane splits, ferrite and magnetics identification |
| 6–8 layer with BGAs | Flight control I/O, ARINC interface board | Two to four weeks | BGA ball mapping, controlled-impedance verification |
| 10–16 layer, HDI or buried vias | Avionics processor, mission computer card | Four to eight weeks | Layer separation on thin cores, via structure correlation |
| Rigid-flex or 20+ layer | Harness-integrated module, backplane | Case by case, usually longest | Flex bend regions, adhesive layers, sheer net count |
| Any of the above + firmware | Locked MCU or configured CPLD on board | Add days to weeks, feasibility-dependent | Part family, protection level, sample quantity |
Two things compress these numbers. Sending two or three identical samples lets us destructively section one while keeping a reference intact, which removes the slowest bottleneck. And telling us the deliverable you actually need — rather than “everything” — often cuts a week of work you were never going to use.
What to send us so the quote is real and not a guess
We can give you a firm price and lead time from photos in most cases. Send this and we will come back with feasibility, price, and a schedule:
- Clear photos of both sides of the board on a dark, non-reflective background. Whole board in frame, edge to edge, straight on. Then a few close-ups of any BGA area, the largest ICs, and any connector with unusual keying.
- Overall board dimensions and thickness, plus layer count if you know it. If you don’t know the layer count, say so — we’ll estimate from the photos and confirm on arrival.
- The markings on the main chips, typed out, including any house numbers or CAGE codes. This is where obsolescence surprises show up early.
- One line on the deliverables you need: Gerber and drill only, Gerber plus BOM, full schematic, netlist, or a working prototype.
- Whether firmware is in scope, and whether you already have the hex file. If you have it, the job gets simpler and cheaper immediately.
- Any legacy documentation you still hold — an old assembly drawing, a partial schematic, an obsolete BOM. Even incomplete records cut hours and improve accuracy.
What comes back from us is a written feasibility assessment, a fixed price for the agreed scope, a lead time, and a note on anything we flagged as risky. If we think a board is a bad candidate, we say so before you ship it.
Where aerospace PCB reverse engineering gets hard, and where it stops
The honest limits matter more than the capabilities list, so here they are.
Cases that are harder but usually workable
Heavily potted assemblies. Boards with staked components and thick epoxy over the tall parts. Rigid-flex with adhesive layers that do not separate predictably. Ceramic substrates and thick-film hybrids, which behave nothing like FR-4 under delamination. Boards where the only sample has already been through a failure and has burned or missing sections — we can often reconstruct from the surviving copper plus the design rules, but it becomes interpretation rather than measurement, and we will tell you which nets are inferred.
Cases where the answer may be no
A single sample of a 16-layer HDI board with no redundancy is a real risk: layer separation is destructive, and if a thin core tears mid-process we may not get a second chance. Custom ASICs and screened parts with no public datasheet can be mapped physically but not functionally characterized. And locked programmable logic varies enormously — on the firmware side, an old 8051 derivative or an AVR with lock bits set behaves very differently from a modern part with a hardened debug interface. Some STM32 devices at the higher RDP level, and MSP430 parts with the JTAG fuse blown, are genuinely difficult and we quote them as feasibility studies rather than guaranteed work. We do not promise a success rate on any specific chip, and we will not take payment for an outcome we cannot see a path to.
The scope creep nobody budgets for
Component obsolescence is the item that most often extends an aerospace project past its original schedule. You recover a perfect file set and then discover four parts on the BOM went end-of-life a decade ago. Planning a form-fit-function substitution, re-verifying the affected circuit, and adjusting the layout is real design work. Budget for it as a possibility from day one rather than treating it as a surprise, and consider having us flag EOL parts during the BOM phase so you see the problem in week two instead of week eight. If long-term supply is the actual driver, a rapid reverse engineering pass focused on documentation first, with the redesign decision deferred, is often the cheaper path.
Frequently asked questions
How much does aerospace PCB reverse engineering cost?
It depends on layer count, component density, and deliverable depth, so we quote per board rather than off a price list. A simple two-lay
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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