Blind and Buried Via PCB Copy | The Hard Parts

Blind and Buried Via PCB Copy — What Makes It Genuinely Difficult

Blind and buried via PCB copy is the process of reverse-engineering a printed circuit board whose layer-to-layer connections include vias that do not pass through the full stackup. A blind via connects an outer layer to one or more inner layers without exiting the opposite surface. A buried via connects two or more inner layers with no visibility from either outside face. Copying these boards accurately requires destructive cross-sectioning, micro-CT scanning, or sequential de-layering—because no amount of backlit photography or standard X-ray reveals the full picture on its own.

Why Standard PCB Copy Methods Fail on HDI Via Structures

On a through-hole-only board, every via is visible from both sides and its connectivity can be confirmed with a continuity probe. Blind and buried vias break that assumption. A 10-layer HDI smartphone module might use laser-drilled microvias (typically 75–100 µm diameter) on layers 1–2 and 9–10, mechanically drilled buried vias on layers 3–8, and staggered or stacked via-in-pad structures connecting them. None of the buried vias appear on the surface Gerber extraction.

Standard optical scanning captures copper patterns on outer layers with high fidelity—0.5 mil (12.7 µm) resolution is routine. But it tells you nothing about what happens between layer 4 and layer 7. If you guess the via structure wrong, the fabricated clone will have open nets or shorted planes, and the board fails at power-on.

Common Failure Modes We See in Botched Copies

• Missed buried vias: Nets appear connected in the outer-layer netlist but are actually routed through an inner buried via that was never captured.
• Wrong drill span assignment: A via that spans layers 2–5 is assumed to be 1–6, causing annular ring violations or shorts to adjacent planes.
• Stacked vs. staggered confusion: Stacked microvias require filled-and-plated processing; treating them as staggered changes the drill program and the lamination sequence.
• Aspect ratio violations: Buried vias with aspect ratios above 8:1 need specific drill parameters. Incorrect stackup reconstruction can push the ratio past reliable plating limits.

How We Perform Blind and Buried Via PCB Copy — 6-Step Process

Step 1 — Non-Destructive X-Ray and Micro-CT Scan

We start with 2D X-ray imaging at 5 µm resolution to identify via locations, then escalate to micro-CT (computed tomography) on critical areas. Micro-CT gives us a 3D volumetric model of the via barrel, revealing its start layer, end layer, and whether it is filled with copper, resin, or left open.

Step 2 — Cross-Section Verification

On a sacrificial sample (or a designated area of the board if only one unit is available), we perform metallographic cross-sectioning. This confirms stackup thickness per layer (dielectric and copper), via drill diameter, plating thickness (typically 18–25 µm for reliable HDI vias), and whether the via is stacked, staggered, or offset.

Step 3 — Sequential De-Layering and Layer Imaging

Chemical or mechanical de-layering exposes each copper layer in sequence. We image every layer at 1200 DPI or higher, then register images to fiducials. For boards with impedance-controlled traces and stackup recovery needs, we also measure trace width and spacing at this stage.

Step 4 — Via Map Construction

Using the combined X-ray, cross-section, and layer-image data, our engineers build a via map that assigns every non-through-hole via a drill span (e.g., L1–L2, L2–L5, L4–L9). This map becomes the drill program’s backbone.

Step 5 — Netlist Extraction and DRC

We extract the netlist from the reconstructed Gerber set and run design-rule checks against IPC-2221B and IPC-6012 Class 2/3 requirements. Every net must match the original board’s continuity. Open or shorted nets trigger a re-check of the via map.

Step 6 — Prototype Fabrication and Electrical Validation

The first prototype run uses the exact lamination sequence and drill spans from the via map. We perform flying-probe testing on 100% of nets and compare against the original board’s measured netlist. Pass rate on first-spin prototypes for our blind-and-buried via projects is typically above 95%; the remaining 5% involve minor drill-span corrections resolved before production.

Typical Specifications and Tolerances

Which Industries Send Us Blind and Buried Via Boards?

HDI boards with blind and buried vias are concentrated in sectors where density matters: smartphones, wearables, medical implants, aerospace avionics, and high-speed networking equipment. We also see them in industrial control systems where legacy HDI boards have gone end-of-life and no original design data exists. Robotics platforms with compact sensor-fusion boards are another growing source—teams working on robotics PCB cloning projects frequently underestimate the via complexity until they see the cross-section.

Blind and Buried Vias vs. Through-Hole Vias — Decision Table

What About Rigid-Flex and Ceramic Substrates with Blind Vias?

Blind and buried vias become even harder to copy when the substrate itself is non-standard. Rigid-flex boards with blind vias across transition zones require extra care because the flex section’s polyimide dielectric behaves differently under laser drilling and chemical de-layering. Via registration shifts at the rigid-to-flex boundary are a known failure point.

On ceramic PCB substrates used in high-reliability applications, vias are often tungsten-filled or silver-filled co-fired structures rather than plated copper. Cross-sectioning ceramic is destructive in a different way—brittle fracture rather than clean polishing—so we use micro-CT as the primary imaging method and reserve cross-sectioning for confirmation only.

What You Need to Send Us

• Minimum 2 board samples — one for non-destructive imaging, one for cross-section. Three is ideal.
• Any existing documentation — even a partial schematic, BOM, or layer stackup note reduces turnaround by 2–4 days.
• Target use case — tell us if this is for legacy production, failure analysis, or redesign so we can optimize the deliverable format.
• Impedance requirements — if the board carries high-speed signals (USB 3.x, PCIe, LVDS), flag it so we prioritize impedance-controlled stackup reconstruction early.

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