Ceramic PCB reverse engineering usually lands in the same price band as a comparable FR-4 board of the same layer count and component density — the substrate itself doesn’t add much cost. What does add cost is thick-film conductor geometry that ignores normal design rules, wire-bonded or unmarked die, and the fact that a ceramic board can’t be delaminated. Lead time for a single-sided or double-sided alumina board is typically a few working days; multilayer co-fired stacks and DBC power modules run meaningfully longer.
Why ceramic boards behave differently under the microscope
The workflow starts the same way as any board — photograph, measure, identify, trace, verify — but three physical facts change the plan.
First, you can’t peel it. On FR-4 we routinely grind or chemically separate layers to image the inner copper. Alumina and aluminum nitride are hard, brittle ceramics; grinding removes conductor and substrate at unpredictable rates and the board tends to fracture rather than yield. So inner-layer work on a co-fired multilayer ceramic board leans on X-ray and careful sectioning of a sacrificial sample instead of layer-by-layer delamination.
Second, the conductors aren’t etched copper of uniform thickness. Thick-film silver-palladium or gold paste screened onto alumina has rounded edges, variable width, and printed resistors that look like nothing on a standard board. A screened R that measures 4.7 kΩ isn’t a component in the BOM — it’s part of the artwork, and it has to be captured as geometry plus a trimmed value, not as a part number.
Third, thermal design is the point of the board. On a DBC power substrate the 0.2–0.3 mm copper pattern, the isolation gaps, and the ceramic thickness are the design. Get the copper weight or the clearance wrong and you’ve recovered a drawing, not a working substrate. We measure copper thickness on a cross-section rather than assuming an ounce figure.
What the engineer is actually looking at
- Substrate identification — alumina (white, opaque, most common), aluminum nitride (gray, used where thermal conductivity matters), beryllia (handled with care and only when the customer already knows what it is), or DBC/AMB copper-on-ceramic.
- Substrate thickness measured with a micrometer at several points, because 0.635 mm and 1.0 mm alumina behave very differently mechanically and thermally.
- Conductor type — thick-film printed paste, thin-film sputtered metallization, or bonded copper. Each implies a different fabrication route for the rebuild.
- Via structure — laser-drilled and filled vias in ceramic are common; plated through-holes are not. Fill material and aspect ratio matter to whoever quotes the fab.
- Die and wire bonds — bare die on ceramic often has no readable marking. Bond pad count, pad layout, and the surrounding circuit are what identify the function.
- Solder resist and overglaze — glass overglaze on thick film is not the same as LPI solder mask and needs to be called out in the fab notes.
What drives the price of ceramic PCB reverse engineering
We won’t publish a number, because a 25 × 25 mm double-sided alumina hybrid and a 150 × 100 mm ten-layer LTCC RF module are not the same job. Here is what actually moves the quote, roughly in order of impact.
| Factor | Effect on cost and time |
|---|---|
| Layer count | Single and double-sided thick film is quick. Co-fired multilayer (LTCC/HTCC) requires X-ray plus destructive sectioning, which multiplies both. |
| Board area and net count | Tracing effort scales with the number of nets and pads, not with board size alone. A dense 30 mm hybrid can outprice a sparse 100 mm substrate. |
| Printed passives | Screened resistors and trimmed values need measurement and geometry capture. Adds engineering hours. |
| Bare die / wire bonds | Unmarked die is the single biggest unknown. Identification may need decapsulation or functional inference. |
| Copper weight (DBC) | Cross-sectioning is required to get real thickness. Small added cost, large added confidence. |
| Deliverable set | Gerber and drill only is the low end. Add schematic, BOM, netlist, fab notes and stack-up drawing and the number rises accordingly. |
| Sample quantity | Two boards let us keep one intact for reference and sacrifice one. One board forces non-destructive-only work, which is slower. |
| Firmware involvement | If a locked MCU on the substrate has to be read, that’s a separate scope with its own feasibility assessment. |
If you want a sense of how these variables move a quote in general, our breakdown of how PCB reverse engineering is priced and scheduled covers the same logic applied to conventional boards, and the ceramic case is the same math with a harder substrate.
How long a ceramic board actually takes
Honest ranges, described the way we’d describe them on a call:
- Single-sided thick-film alumina, discrete parts, no bare die. Fast. Photography, dimensional measurement, conductor tracing and file generation are straightforward. A few working days.
- Double-sided alumina with vias. Add via mapping and registration between sides. Still short, usually under a week for a moderate net count.
- DBC or AMB power substrate. Geometry is simple, but cross-sectioning for copper and ceramic thickness plus fab-note work adds a step. Short to medium.
- Hybrid with bare die and wire bonds. The circuit tracing is manageable; identifying the die is the schedule risk. Medium, with a genuine possibility that one part stays as a functional block rather than a part number.
- Co-fired multilayer LTCC/HTCC. The long case. Inner conductors have to be imaged, sectioned, correlated and re-correlated. Plan on a multi-week engagement and expect us to ask for more than one sample.
Two things compress the schedule more than anything else: sending more than one board, and telling us up front which deliverables you actually need. A customer who says “Gerber and drill for refab, no schematic needed” gets files far sooner than one who leaves the scope open.
What to send us, and what you get back
Before any quote, send this. It takes five minutes and it’s the difference between a real number and a placeholder.
- Clear photos of both sides, whole board in frame, shot on a dark background with even light. Ceramic is bright and reflective — dark background, no flash, hold the camera square to the board.
- Board dimensions — length, width, and substrate thickness if you can measure it. A caliper reading beats an estimate.
- The markings on any packaged chip, typed out, including the line breaks. If there’s only bare die, say so and photograph the bond pattern.
- One line on deliverables: files for refabrication, a schematic for maintenance, a BOM for sourcing, or all three.
- Whether the board is known-good or failed, and how many units you have.
What comes back from us: a feasibility assessment naming any part or layer we’re unsure about, a lead time, and a price. Not a brochure. On delivery you typically receive Gerber and drill data, a stack-up and material note that specifies substrate type and thickness rather than defaulting to FR-4, a BOM with any printed passives listed as artwork, and — if scoped — a schematic and netlist. Our summary of what a completed reverse engineering package contains lists the file formats in detail.
Where ceramic PCB reverse engineering gets hard, and where it stops
The cases we push back on, or scope carefully:
Unmarked bare die. If a hybrid contains a custom die with laser-marked house numbering, we can map every bond wire and still not be able to tell you what to buy. Sometimes the die is a recognizable standard part in a chip-on-board package; sometimes it’s an ASIC that only ever existed for that product. We say which case you’re in before you commit money.
Single-sample multilayer LTCC. With one board and no permission to destroy it, inner-layer recovery on a co-fired stack is limited to what X-ray resolves. That’s often enough for a four-layer stack and often not enough for ten. We’d rather tell you that than deliver a plausible guess.
Trimmed thick-film resistors. A laser-trimmed resistor’s measured value depends on the trim cut, and the as-printed value is different from the as-trimmed value. We report both where we can measure them, but if the network was trimmed in circuit against a calibration target, the rebuild will need its own trim step.
Thermally damaged or cracked substrates. A failed power module with a cracked ceramic and delaminated copper may have lost the very geometry you need. A second, intact reference unit solves this instantly.
Legitimate use. Almost all of this work is maintenance-driven: keeping out-of-production industrial and medical equipment alive, replacing an obsolete substrate, analyzing a field failure, or recovering files for a design you own but whose CAD data is gone. You’re responsible for holding the rights to the design and for complying with applicable IP law; we work under NDA on every project. That’s the whole of it.
FAQ
Can you reverse engineer a ceramic PCB without destroying it?
Usually yes for single and double-sided thick-film boards — photography, microscopy, X-ray and electrical probing get there without damage. Co-fired multilayer ceramic is different: inner conductors can’t be reached mechanically without sectioning. If you can supply two units, we keep one intact and sacrifice the other, which shortens the schedule and improves acc
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