Circuit Board Cloning: Cost and Lead Time Explained

Circuit board cloning is priced per board, not per hour, and the two numbers that move it most are layer count and component count. A small two-layer control board with a hundred passives and a handful of ICs is a modest job measured in days. A dense eight-layer board with fine-pitch BGAs, a locked microcontroller, and no silkscreen left on it is a different order of work entirely. Below is what actually drives both the quote and the calendar.

What you get for the money, and what “clone” means here

Cloning a board means producing a manufacturable copy of it. In practice that breaks into three deliverable tiers, and the tier you pick changes the price more than anything except layer count.

• Gerber-level copy. Copper, solder mask, silkscreen, drill file, stackup. Enough to order bare boards that drop into the same enclosure with the same connector positions. No schematic.
• Full electrical recovery. Gerbers plus a netlist, a readable schematic, and a bill of materials with real part numbers and package sizes. This is what you need if anyone will ever modify the board.
• Working assembly. Everything above plus sourced parts, assembly, and functional test against the original board’s behavior.

Most maintenance and obsolescence work stops at tier two. If you only need spare bare boards for a legacy machine, tier one is cheaper and faster, and there is no reason to pay for schematic capture you will never open.

The seven things that set the price

Nobody can quote a board from a description. But you can predict roughly where your board lands by looking at these, in rough order of impact:

1. Layer count. Two layers can be imaged from both sides. Four layers and up means the inner layers have to be exposed and imaged separately, which is destructive, sequential, and slow. This is the single biggest cost step.
2. Component count and density. Every part has to be identified, located, and entered. Six hundred components is roughly six times the data entry of a hundred, regardless of how simple the circuit is.
3. BGA and fine-pitch parts. Ball grid arrays hide their connections. Escape routing under a 0.5 mm pitch BGA has to be traced from inner-layer images and confirmed with X-ray, which adds real hours.
4. Board size. A 300 mm backplane needs more imaging tiles, more stitching, and more registration checks than a 40 mm module.
5. Whether firmware is involved. If a programmed microcontroller has to come out of the board and the code has to be read, that is a separate scope with its own feasibility question. It is quoted apart from the board work.
6. Condition of the sample. A clean, unconformal-coated, unpotted board with legible markings is cheap. A burnt board with lifted pads, or one under epoxy potting, costs more because reconstruction time replaces measurement time.
7. Deliverable set. Gerbers only, versus Gerbers plus schematic plus BOM plus pick-and-place. Each added file is real engineering time, not a checkbox.

If budget is the constraint, tell us up front. There are usually legitimate ways to trim scope — one board instead of the whole set, Gerbers now and schematic later, skipping the assembly stage — and a good PCB copy company will tell you which cuts are safe and which ones will bite you at production.

How long a two-layer board takes versus an eight-layer BGA board

Turnaround follows the same drivers as price, with one difference: layer separation is sequential and can’t be parallelized much. Once you’re past four layers, calendar time grows faster than cost does.

Rush handling exists and it is real — we reorder the queue and put more than one engineer on the imaging and entry stages. What rush cannot do is compress the physical steps. Grinding down to layer three and imaging it takes the time it takes.

Why more than one sample helps

Layer separation destroys the board. If you send one sample and it’s your only one, we work more conservatively and slower, because there is no second chance at an inner layer. Two or three identical boards let us cross-check ambiguous traces and usually shortens the schedule. If you can only spare one, say so — it changes how we plan, not whether we take the job.

What happens to your board, step by step

This is the part most vendors leave vague, so here is the actual sequence.

Intake and photography. The board is weighed, measured, and photographed at high resolution on both sides before anything touches it. Connector positions, mounting hole centers, and board outline are dimensioned first, because those are the features that have to match the enclosure and they’re the ones you can’t recover after grinding.

Component identification. Every part gets read, and marked parts get cross-referenced to a real manufacturer part number. Unmarked passives get measured — capacitance, resistance, inductance — and package size is taken from the footprint. This is where obsolescence usually surfaces: a regulator or an optocoupler that went end-of-life years ago, which we flag in the BOM with candidate replacements rather than silently substituting.

Desoldering and cleaning. Parts come off, the board is cleaned, and any conformal coating is removed. Now the copper is visible.

Imaging and layer separation. Outer layers are scanned. For multilayer boards, material is removed layer by layer and each inner layer is imaged with alignment fiducials so the stack registers correctly. Drill locations and via types are recorded as we go. BGA regions get X-rayed before separation so we have an independent reference for the escape pattern.

Rebuild in CAD. Copper is redrawn as real objects — pads, tracks, planes, drills — not traced bitmaps. Trace widths and clearances are measured, not guessed, so that power traces keep the current capacity the original designer intended and impedance-controlled pairs keep their geometry against the reference plane.

Verification. The recovered netlist is checked pin-to-pin against the physical board with a continuity meter on a sampled basis, and against the imaged layers node by node. DRC runs against the recovered stackup. Where the original board’s workmanship class matters — plating thickness, annular ring, hole registration per IPC-A-600 and IPC-6012 — we call it out in the stackup notes so your fabricator builds to the same class rather than the cheapest one.

Optional build and test. If the scope includes it, we fabricate, assemble, and run the new board against the original’s measured behavior. Same rails, same timing, same outputs under the same load.

What to send us for a real quote

You don’t need to ship the board to get a price. Send this and you’ll get feasibility, lead time, and cost back rather than a request for more information:

• Photos of both sides, whole board in frame, shot square-on against a dark background, in focus. Then close-ups of any IC whose marking is small or partly worn.
• Board dimensions — length, width, and thickness — plus layer count if you know it.
• The main chip markings, typed out exactly as printed, including the line under the part number.
• One line on deliverables: Gerbers only, Gerbers plus schematic and BOM, or a working assembled board.
• Quantity and use case. Ten spares for a legacy line and a thousand units a month are different engineering decisions.

The photo quality genuinely matters. A dark background and even lighting let us count layers from the board edge, read silkscreen, and spot BGAs and potting before the board arrives. Blurry phone shots on a white desk under a ceiling light cost you a day of back-and-forth. If you specifically need manufacturing data and nothing else, the process of generating Gerber files from a finished board is the narrowest and cheapest path.

Where circuit board cloning gets hard, and where it stops

Honest limits, because these change the answer:

Potted and epoxy-filled assemblies. Removing potting without destroying what’s underneath is possible but slow, and sometimes the parts come out unreadable. We’ll tell you the odds before you commit.

HDI with stacked microvias. Feasible, but mapping which microvia lands on which pad in a stacked structure is painstaking. Expect this to be quoted individually, never off a standard rate card.

Sanded or laser-scrubbed part markings. When a designer has deliberately removed IC markings, identification moves to pinout behavior, package, and circuit context. Sometimes that’s conclusive. Sometimes we can only narrow it to a family, and we say so instead of guessing on your BOM.

Locked microcontrollers. Copying the board copies the hardware, not the program. Whether the code can be read depends entirely on the specific part and how it was protected — an STM32 at RDP level 1 is a different situation from one at level 2, an MSP430 with a blown JTAG fuse is different from one with only a BSL password, and 8051 and AVR parts vary by lock-bit configuration and die generation. Nobody honest guarantees a locked part in advance. We assess the specific chip and give you a real yes, no, or maybe.

Custom ASICs, unm