For a communication board, PCB copy is less about tracing nets and more about reproducing the electrical environment those nets live in. A line card, radio front end, or base station power module only works if the stackup, dielectric constant, trace geometry, and ground referencing match the original. So a proper communication PCB copy starts with layer separation and impedance measurement, not with a scanner and a hopeful guess.
That single difference is why a telecom board and a thermostat board can have the same layer count and the same net count, and take very different amounts of time.
What makes communication boards different from ordinary board duplication
Most industrial boards tolerate small deviations. A 6-mil trace that comes back at 6.4 mil in a motor driver still drives the motor. On a communication board carrying a differential pair at multi-gigabit rates, or a 50-ohm microstrip feeding an amplifier, that same 0.4 mil moves the impedance and shows up as return loss.
Practical consequences we run into on almost every telecom job:
- Mixed materials. Hybrid stackups are common — a low-loss laminate for the RF layers bonded to standard FR-4 for the digital and power sections. If you copy the copper and ignore the dielectric, the RF section is wrong.
- Blind and buried vias. High-density telecom boards route out of fine-pitch BGAs with microvias and via-in-pad. The drill file has to be reconstructed per layer pair, not as a single through-hole set.
- Reference plane continuity. Where a plane is deliberately cut, or deliberately solid under a pair, matters. Those decisions have to be captured as they are, not tidied up.
- Copper thieving and dummy pads. Non-functional copper on communication boards is usually there for plating uniformity or RF grounding. Removing it looks cleaner and behaves differently.
- Connector and shielding geometry. SFP cages, RF coax launches, edge-plated grounds, and board-edge gold fingers all have mechanical tolerances tied to the enclosure.
How a communication PCB copy actually runs, step by step
1. Intake and non-destructive capture
The board is photographed, measured, and X-rayed before anything is touched. X-ray tells us via structure, whether there are buried layers, and what is hiding under BGAs and shield cans. Board thickness is measured with a micrometer at several points, and outline dimensions plus mounting hole positions are recorded against the original.
2. Component identification
Every part gets identified from marking, package, and in-circuit measurement. On communication hardware this is where most of the real work sits: SerDes chips, PHYs, clock generators, PLLs, VCOs, filters, baluns, and SAW devices often carry house-marked or laser-scrubbed part numbers. Passives in the RF path get measured, because a 0402 that looks like a capacitor may be a specific Q-factor RF part.
3. Layer separation and net tracing
The board is delayered, and each copper layer is imaged separately and vectorized. Inner-layer imaging is the reason a 10- or 12-layer board takes meaningfully longer than a 4-layer one — the count of images, alignments, and via-to-via correlations grows with every layer. Nets are then rebuilt and cross-checked against continuity measurements taken on the original board before delayering.
4. Stackup and impedance reconstruction
Measured dielectric thicknesses, copper weights, and trace widths go into an impedance solver so the reconstructed stackup produces the same target impedances the original was designed for. Where the original used a low-loss laminate, we identify the closest available material and state it explicitly rather than silently substituting FR-4. Design rules are checked against IPC-2221 and IPC-2222 conventions, and current-carrying traces are sanity-checked against IPC-2152 guidance.
5. Output generation and verification
Gerber or ODB++, drill files, netlist, BOM, and pick-and-place come out of the rebuilt data. Fabricated bare boards are inspected to IPC-A-600 for visual acceptability and IPC-6012 for performance class, with the class chosen to match how the original was built. Then a netlist comparison runs the new board against the extracted netlist — that catches the errors human eyes miss.
6. Assembly and functional check
If you want a working board back, the first article is assembled and tested. For communication hardware, the meaningful test is link-level: does the port come up, does it hold sync, does the RF section hit the same output power and spectral mask as the reference unit. Continuity alone proves nothing about a 10 Gb/s lane.
Which deliverable set you should actually ask for
Not every project needs the full package. Choosing correctly saves you real money.
| Deliverable set | What you get | Right for |
|---|---|---|
| Fabrication data only | Gerber/ODB++, drill, stackup, netlist | You need more of the same board built, no design changes planned |
| Fab data + BOM | Above, plus a sourced bill of materials with package and value data | You will assemble elsewhere, or need to check part availability first |
| Full reverse engineering | Editable schematic, block-level function notes, netlist, layout source | You plan to modify, replace an obsolete PHY, or maintain the design long-term |
| Turnkey | All of the above plus assembled, tested boards | Field replacement units needed now for equipment still in service |
If a line card is failing in the field and the vendor no longer supplies it, fab data plus assembly is usually enough. If your obsolescence problem is a discontinued Ethernet PHY, you need the schematic, because you are going to redesign that section. The same logic applies across adjacent sectors — the reasoning behind choosing deliverables for instrumentation boards is nearly identical, since both live and die on signal integrity.
What to send us, and what comes back
Quotes get accurate fast when the intake is good. Send this:
- Clear photos of both sides of the board, on a dark, non-reflective background, whole board in frame, in focus, with even lighting. Shoot straight down, not at an angle.
- Board dimensions — length, width, and thickness — plus the layer count if you know it.
- Close-ups of the main chip markings, especially the SerDes, PHY, baseband, or MCU. If a marking is scrubbed, say so.
- One line on deliverables: fab files only, files plus BOM, full schematic, or assembled boards.
- Quantity and timing, if you already know them. Five spares and five thousand units lead to different recommendations.
What comes back from us is a feasibility assessment naming any specific risks we can see in the photos, a lead time, and a price. If the photos suggest something we cannot judge remotely — potting compound, a suspected embedded component, a shield can we cannot see under — we say that instead of guessing, and ask for the physical sample.
Honest limits on communication board work
Some of these are hard limits, some just change the cost and schedule.
- Exotic laminate matching. We can identify the class of material and its measured Dk/Df behavior, but if the original used a laminate that is now discontinued or export-restricted, you get a nearest available equivalent and a note about the expected difference. That is a substitution, and we label it as one.
- Programmable logic contents. A telecom board with an FPGA or CPLD is only a partial copy without the configuration bitstream. Getting that is a separate question with its own feasibility answer, and it depends heavily on the part family and its security settings.
- Protected firmware. Where a management MCU holds firmware you own but no longer have source or hex for, recovery may be possible depending on the family and its protection state — STM32 RDP level, MSP430 JTAG fuse and BSL password state, lock bits on 8051 and AVR parts all change the answer. Nobody honest promises a specific chip in advance.
- Potted and conformally coated assemblies. Removable, usually, but it costs sample boards and time, and there is real risk to the reference unit.
- Single damaged sample. One badly corroded or burned board makes some nets unreadable. Two samples, even mismatched revisions, dramatically improve the outcome.
- Licensed silicon. Some communication ICs are only sold to approved OEMs. Reproducing the board does not solve a procurement wall, and we will flag it during quoting rather than after.
Boards from other high-reliability sectors bring similar trade-offs — the constraints we describe for defense-sector board duplication overlap closely with telecom infrastructure work, particularly around obsolete parts and material substitution.
Legitimate use, and confidentiality
The communication PCB copy work that comes through our lab is overwhelmingly maintenance-driven: keeping installed base stations, multiplexers, PBX systems, radio links, and test sets running after the vendor ended support; replacing an obsolete PHY or clock chip; recovering design data for a product whose original files vanished with a former engineering team; and failure analysis on units that died in the field. Recovering firmware you own but lost, and keeping connected devices serviceable past their vendor support window, fall in the same category.
You are responsible for holding the rights to the design you send, and for complying with applicable IP and export law in your jurisdiction. Every project runs under NDA, samples and data stay inside the lab, and we do not retain or reuse customer design files after handover.
FAQ
Can you copy a communication PCB without the original schematic?
Yes. The physical board is the source of truth. Nets come from delayering and imaging, values come from
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote