A double-sided PCB copy means recovering the top and bottom copper, the drill pattern, the silkscreen, and the parts list from a physical two-layer board, then rebuilding it as manufacturable files. On a clean two-layer board it’s the most predictable job in this business — no layer separation, no blind vias, every trace visible under a microscope once the solder mask is dealt with. The hard parts are almost never the routing. They’re the parts you can’t see: what’s under the connectors, what the unmarked SOT-23 actually is, and whether the copper you’re tracing was hand-tuned for a reason.
What actually happens to your board, in order
Assume you’ve sent one populated board and, ideally, one bare board. Here’s the sequence.
- Intake and photography. The board gets logged, measured with calipers, and photographed on both sides under diffuse light. Board outline, mounting hole positions, and connector datum points get recorded before anything is touched, because that’s the geometry the finished board has to drop into.
- Component identification. Every marking is read and logged — value, package, polarity, orientation. Passives get metered where the marking is ambiguous. Unmarked or house-numbered parts get flagged for in-circuit analysis rather than guessed at.
- Desoldering. Parts come off in a controlled order so the reference designator map stays intact. Electrolytics and connectors go last because they anchor the mechanical reference.
- Copper imaging. The bare board is cleaned, the mask is removed or made transparent depending on the finish, and both sides are scanned at high resolution against a registration target so top and bottom images share the same origin.
- Vector rebuild. The scans get traced into real geometry — pads, tracks, planes, drills — not bitmaps traced by a filter. Track widths and clearances are measured, not eyeballed, because trace width carries information about current (the reference for that is IPC-2152) and clearance carries information about working voltage.
- Netlist verification. This is the step that separates a copy that works from a copy that looks right. The extracted netlist is compared, node by node, against continuity measurements taken on the original bare board. Every net gets confirmed by meter, not by assumption.
- Output and check plot. Gerbers, drill file, pick-and-place, BOM, and silkscreen artwork are generated, then compared against the original as an overlay at 1:1.
If you also want a readable circuit diagram out of it — not just copper — that’s a separate deliverable tier, and worth deciding up front. The full breakdown of what lands in your hands at handover covers which files come with which tier.
Why the second side changes the math
Compared to a single-layer board copy, the added work in a double-sided job isn’t doubled copper. It’s registration and vias.
Registration
Top and bottom images have to align to within a fraction of a pad radius. Get it wrong by 4 mil and your through-hole pads land off-center on the bottom side, annular ring goes out of spec per IPC-A-600, and the fab either flags it or builds a board with breakout. Registration is done from drilled features that exist on both sides, not from the board edge, because the edge was routed and has its own tolerance.
Vias that aren’t really vias
On a two-layer board, plenty of “vias” are actually component holes doing double duty, and plenty of pads look connected on one side and aren’t. Thermal reliefs, stitched ground returns, and single-point star grounds on analog sections all look like noise in a scan and are deliberate in the design. Those have to be read as intent, not just copied as pixels.
Copper pours
Two-layer boards frequently use a bottom-side ground pour with deliberate slots to steer return current. Redrawing that pour as a solid fill is the single most common way a well-traced copy fails EMC on a switching supply or a motor drive.
The double-sided boards that give us trouble
Being honest about this saves everyone a week. Two-layer doesn’t automatically mean easy.
- Conformal coating or potting. Coating can usually be removed chemically with care. Full epoxy potting is a different problem — sometimes the board survives, sometimes it doesn’t, and we’ll tell you the risk before touching it.
- Heavy copper. Two-ounce and up etches with rounded sidewalls, so measured track width is not the drawn width. We back-calculate, but tell us if the board is a power stage so we compensate correctly.
- Damaged or lifted traces. A burned board can still be copied, but a trace that’s vaporized has to be reconstructed from circuit logic. That’s engineering judgment, and we mark every reconstructed net as reconstructed rather than pretending it was measured.
- Unmarked and house-marked ICs. Laser-blanked parts and custom part numbers mean we identify by pinout behavior and package. Sometimes that lands on a definite answer, sometimes on a short list of candidates. It’s the most common reason a quote comes back with a caveat.
- Single-sided-looking boards with hidden jumper wires. Common on older consumer and appliance boards. Factory rework wires get logged, but you need to tell us whether you want them baked into the layout or left as rework.
- Locked microcontrollers. Copper and BOM recovery has nothing to do with firmware. If the board only functions with the code inside a protected MCU, that’s a separate scope with a separate feasibility answer.
- Boards where somebody already tried. Half-desoldered parts and lifted pads make identification and continuity work slower, not faster.
How a double-sided job compares to a denser board
| Aspect | Double-sided (2 layer) | 4–8 layer | HDI / microvia |
|---|---|---|---|
| Layer separation needed | No | Yes — controlled delamination | Yes, plus X-ray |
| Board consumed in process | Usually survivable | One sample destroyed | One or more destroyed |
| Main risk | Misidentified parts, pour intent | Inner-layer registration | Buried via mapping |
| Samples we prefer | 1 populated + 1 bare | 2 minimum | 2–3 |
| Relative lead time | Shortest | Noticeably longer | Longest |
If it turns out your board isn’t actually two-layer — and buried planes on thick boards fool people regularly — the work shifts into dense multilayer territory with a different process. We check layer count on arrival and re-quote before starting, not after.
What to send us, and what you get back
Send this to get a real quote
- Clear photos of both sides of the board on a dark background, whole board in frame, in focus, taken straight-on rather than at an angle
- Board dimensions — length, width, thickness
- A readable close-up of the main IC markings, especially any microcontroller
- One line telling us which deliverables you need: Gerbers only, Gerbers plus BOM, or full schematic recovery too
- Whether you plan to build the board as-is or modify it later — that changes whether we deliver a flat copy or an editable native CAD database
What comes back from us
A feasibility statement in plain language, including anything we can’t promise; the deliverable list; a lead time; and a price. If a component looks unidentifiable from photos, we say so in the quote instead of discovering it mid-project and asking for more money.
What we hand over at the end
Gerber set (RS-274X), NC drill file, IPC-D-356 or netlist export, BOM with reference designators and package data, pick-and-place file, and — if it’s in scope — a schematic drawn to be read by a human, with power rails grouped and functional blocks separated instead of dumped as a rat’s nest.
What drives the price and the schedule
Nobody can quote a double-sided PCB copy from a description alone. What moves the number:
- Component count. A 40-part control board and a 400-part board are different jobs even at the same layer count. Identification and BOM work scales with part count, not board area.
- Board area and track density. Fine-pitch QFN and 0402 passives slow down both scanning and verification.
- Deliverable depth. Gerber-only is the cheapest path. Schematic recovery costs more because every net has to be understood, not just traced. Editable native CAD adds more again.
- Board condition. Coating, corrosion, burn damage, prior rework.
- Whether firmware is in scope. Completely separate feasibility question with its own timeline.
- Number of samples supplied. One board means we work conservatively. Two means we can be destructive with one and keep a reference.
On timing: a clean, low-count two-layer board with legible markings is typically a matter of days. A dense two-layer board with unmarked parts and a schematic deliverable runs meaningfully longer, mostly because of identification and verification rather than drawing. Anyone quoting a fixed turnaround before seeing photos is guessing.
Legitimate use, and confidentiality
The double-sided boards that come through here are mostly obsolete industrial controllers nobody can buy anymore, boards whose original Gerbers left with a contractor years ago, in-house designs where the CAD archive was lost in a server migration, and failure analysis on units returning from the field. Component obsolescence is the other big one — you need the layout in editable form to swap a discontinued regulator for something still in production.
You need to hold the rights to the design you’re asking us to repro
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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