With HDI PCB reverse engineering, the thing that changes with layer count isn’t just “more work.” It’s that HDI boards use microvias and blind/buried via structures, so the layer stack has to be reconstructed as a build-up sequence — which cores were laminated first, which sublaminate got drilled next — not just as a list of copper layers. An 8-layer 1+N+1 board and a 12-layer 3+N+3 board are different jobs, and the second one takes meaningfully longer.
If you’re holding a dead controller board with a laser-drilled stack and no design files, this page tells you what actually happens to it, what we need from you, and where the honest limits are.
Why HDI boards behave differently from ordinary multilayer
On a conventional 4- or 6-layer board, every via is a through-hole. Once you’ve imaged the copper on each layer, connectivity follows from hole positions, because a hole at a given X/Y connects everything it passes through. That assumption dies on HDI.
An HDI stack has laser-drilled microvias — often 75–125 µm finished diameter — that connect only adjacent layer pairs. They may be stacked directly on top of each other, staggered, or dropped onto a buried via in the core. Two vias at almost the same coordinate can belong to completely different nets on different layer pairs. So the reconstruction has to answer three questions per via, not one: which two layers does it join, is it a laser microvia or a mechanically drilled hole, and is it filled and capped.
That’s the part that scales badly with layer count. Copper imaging scales roughly linearly. Via classification scales with the number of build-up levels, and a 3+N+3 structure has three levels of microvia on each side to resolve before you can trust the netlist.
The other HDI-specific complications
- Fine geometry. Trace/space in the 50–75 µm range means high-magnification imaging and careful handling of copper edge definition. What looks like a 3-mil gap under a loupe can be a short at 2000 dpi.
- Via-in-pad. BGA pads with microvias in them hide connectivity under the solder ball. You can’t probe it; you have to remove the component and then image, or X-ray first to see where the via lands.
- Thin dielectrics. Build-up layers are often 50–75 µm of resin-coated copper. Mechanical delamination is unforgiving — one aggressive pass and you’ve destroyed the layer you needed.
- Impedance. HDI boards usually carry differential pairs at real speeds. Dielectric thickness and Dk have to be measured, not guessed, or the rebuilt board won’t behave like the original.
How HDI PCB reverse engineering actually runs, step by step
- Intake and documentation. Both sides photographed at high resolution before anything is touched, board dimensions measured, every component marking recorded. Nothing gets removed until the as-received state is documented.
- X-ray. On HDI this comes early, not late. 2D X-ray shows via patterns under BGAs and land grid arrays; CT or oblique imaging helps distinguish stacked from staggered microvias and finds buried structures in the core. This is where we build a first hypothesis about the build-up: 1+N+1, 2+N+2, 3+N+3, or asymmetric.
- Component removal and identification. Parts come off hot air or with a rework station, get logged by position, and marking-to-part-number resolution happens for each. Sanded or laser-remarked ICs are flagged here rather than guessed at.
- Cross-section. A coupon from a non-critical edge region is potted, ground, polished and imaged. This gives real numbers: copper thickness per layer, dielectric thickness per layer, via geometry, plating thickness, and whether microvias are filled. Layer count gets confirmed here — X-ray estimates on HDI are sometimes off by one buried pair.
- Layer separation and imaging. Controlled delamination or sequential grinding, layer by layer, with each copper layer scanned before the next is removed. On a build-up structure the order matters: you work outward-in, and each removal step gets a registration check against the drill pattern so layers stay aligned.
- Vectorization and stackup rebuild. Scans convert to copper polygons, drill and laser-via data get assigned to layer pairs, and the whole thing is assembled into a stackup with real dielectric values.
- Netlist verification. The rebuilt netlist gets checked against continuity measurements taken on the physical board wherever pads are still accessible, plus a design-rule pass. Discrepancies get run down individually, not averaged out.
- Deliverables. Gerbers or ODB++, drill files split by via type, stackup documentation with impedance targets, BOM, and schematic if that’s in scope.
The verification step is where HDI jobs earn or lose their credibility. A netlist that hasn’t been cross-checked against physical continuity on an HDI board is a hypothesis, not a result.
What layer count and build-up structure do to the schedule
Two boards with the same layer count can differ by a factor of two in effort if one is a simple 1+N+1 and the other has three build-up levels per side with stacked, filled microvias. Here’s roughly how the classes compare.
| Structure | Typical layers | What drives the effort | Relative effort |
|---|---|---|---|
| 1+N+1 | 6–8 | One microvia level per side; core is conventional through-hole | Baseline for HDI |
| 2+N+2 | 8–12 | Stacked vs. staggered decision on two levels; buried vias in core | Noticeably higher |
| 3+N+3 and above | 12–20 | Three build-up levels, filled/capped vias, dense via-in-pad under multiple BGAs | Substantially higher |
| Any-layer / ELIC | 10+ | Microvias at every interface; via classification dominates the job | Highest; feasibility assessed case by case |
Board area and BGA count push in the same direction. A small 10-layer HDI module with one BGA is a shorter job than a large 8-layer board with four fine-pitch packages and via-in-pad everywhere. If you want a sense of how the arithmetic looks on straight multilayer without the microvia complication, the same logic plays out on power board reconstruction where copper weight rather than via density is the driver.
What to send us, and what comes back
Feasibility on HDI is mostly determined in the first ten minutes of looking at photos, so send these:
- Clear photos of both sides, whole board in frame, on a dark non-reflective background, with the board filling most of the shot.
- Close-ups of any BGA or fine-pitch area, plus a shot of the board edge if you can get one — edge plating and layer lines are informative.
- Board dimensions and overall thickness. Thickness plus layer count already tells us a lot about the dielectric budget.
- The markings on the main ICs, typed out rather than left to be read from a blurry photo.
- One line on what you need: Gerbers only, Gerbers plus BOM, schematic as well, or a working assembled board at the end.
- Whether you can supply more than one board. On HDI this matters more than on any other board type — see below.
What you get back: a feasibility read on the structure, a lead time, a price, and a note on anything we expect to be a problem. If the board looks like a case where cross-section will change the answer, we say that up front rather than after you’ve paid.
Why we ask for two or three boards
Layer separation on HDI is destructive. Thin build-up dielectrics don’t always release cleanly, and a cross-section coupon consumes real board area. With one sample, a bad delamination pass on layer 5 of 12 costs you the project. With two or three, we can cross-section one, keep one for continuity reference with components still installed, and separate the third. If only one board exists, we shift to a more conservative and slower sequence — X-ray heavily, probe everything reachable, then commit — and the schedule reflects that.
Where HDI reverse engineering gets hard, and where it stops
Being straight about this is more useful to you than a promise.
- Stacked microvias on thin resin. Distinguishing a stacked pair from a staggered pair sometimes needs CT plus a targeted cross-section through that exact location. If the stack sits under a BGA in a congested region, we may have to sacrifice board area to be sure.
- Buried via detail in the core. Filled buried vias with copper-filled resin can read ambiguously on X-ray. Cross-section resolves it, but only where you cut.
- Heat and moisture damage. A board that’s been through a thermal event may already be delaminated internally. Layers separate unpredictably and copper can lift with the resin.
- Conformal coating and potting. Coating is workable. Full epoxy potting on an HDI assembly is the worst combination we see — removal risks the fine geometry underneath.
- Remarked or custom silicon. An ASIC with no public datasheet, or a house-numbered part, limits how complete a schematic can be. We document pin connectivity and function where it’s inferable and mark the rest as unresolved rather than inventing a part number.
- Firmware. Copper reconstruction gives you a board, not a working product. If a locked microcontroller holds the code, that’s a separate engineering question with its own feasibility depending on the exact part and its protection state — STM32 RDP level, an MSP430 JTAG fuse, and 8051-family lock bits are all different problems.
Design rules are checked against IPC-2221 and IPC-2222 conventions, and acceptability of the boards we build from the recovered data is judged against IPC-A-600 and IPC-6012 class 2 or 3 depending on what the application requires. On current-carrying traces we sanity-check widths against IPC-2152 rather than assuming the original layout was correct.
Working on a board like this?
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