HDI PCB Copy — What Makes It Genuinely Difficult
HDI PCB copy is the process of reverse-engineering a high-density interconnect board — extracting Gerber files, a complete BOM, and a verified stackup — from a physical sample that uses microvias, blind/buried vias, and trace/space geometries below 4 mil. Unlike standard multilayer cloning, HDI boards compress routing density into fewer layers using sequential lamination cycles, and every one of those cycles introduces tolerances that a careless copy will miss. Our engineers treat each lamination stage as a separate sub-project because that is what it takes to produce a functional clone.
Why Standard Reverse-Engineering Methods Fall Short on HDI
A typical 4- or 6-layer FR-4 board can be cross-sectioned, photographed layer by layer, and digitized with a reasonable margin for error. HDI boards break that workflow in three specific ways:
- Stacked and staggered microvias. A via-in-pad structure with stacked microvias across three or more layers cannot be resolved from top/bottom imaging alone. We need sequential de-lamination, controlled etching, and high-resolution cross-sectioning at multiple points to map the full via tree.
- Sub-3-mil trace and space. HDI designs routinely use 2.5/2.5 mil (63/63 µm) or tighter. Optical scanning at standard resolution aliases these traces. We use 50,000+ DPI scanning with algorithmic edge detection to capture accurate widths.
- Sequential lamination stackups. An 8-layer HDI board built with 2+4+2 construction has different dielectric thicknesses between core layers and buildup layers. Measuring these with a micrometer after delamination is not optional — impedance depends on it.
These factors compound. A 10-layer board with two sequential lamination cycles, stacked microvias, and 0.4 mm-pitch BGA escape routing has roughly 4× the failure modes of a conventional 10-layer through-hole-via board.
How We Execute an HDI PCB Copy — Layer by Layer
Step 1: Non-Destructive Analysis
Before anything is cut or etched, we X-ray the sample board to map all via structures — blind, buried, stacked, staggered — and identify the lamination sequence. This X-ray map becomes our reference for every subsequent step. We also run an impedance profile on accessible transmission lines to establish baseline targets.
Step 2: Component Removal and BOM Extraction
Every component is catalogued with manufacturer part number, package footprint, and orientation. Fine-pitch BGAs (0.4 mm and below) get special attention — we record ball count, pad diameter, and solder mask opening size because these directly affect the escape routing under BGA packages in the Gerber output.
Step 3: Sequential Delamination and Layer Imaging
We delaminate the board one buildup layer at a time, starting from the outermost. Each copper layer is imaged at high resolution, then the exposed dielectric is measured for thickness at a minimum of five points per layer. Core layers are separated last. The result is a complete photographic record of every copper layer plus verified dielectric data for the stackup.
Step 4: Via Structure Mapping
Microvias are verified by cross-section at multiple locations. We measure drill diameter (typically 75–150 µm for laser-drilled microvias), capture depth, pad diameter, and land size. Stacked microvias get additional attention — copper fill quality and target pad registration are documented because these affect reliability in the clone.
Step 5: Digitization, DRC, and Impedance Simulation
Layer images are converted to Gerber data. We run a full design-rule check against the measured stackup, then simulate impedance for every identified differential pair and single-ended controlled-impedance trace. If simulation results deviate more than ±5% from the measured baseline, we adjust dielectric values or trace widths until they converge.
What Is the Via Aspect Ratio — and Why It Matters for HDI Cloning
The drill aspect ratio — the ratio of hole depth to diameter — determines whether a via can be reliably plated. Standard through-hole vias in production typically stay below 10:1. HDI microvias are usually 0.8:1 to 1:1 for single-layer laser vias, but stacked structures spanning multiple layers can push effective aspect ratios higher. If your HDI PCB copy specifies a via structure that exceeds your fabricator’s plating capability, you get voids, opens, or reliability failures.
Use the calculator below to check whether your via dimensions are within standard plating limits before committing to fabrication:
PCB manufacturing
Drill Aspect Ratio Checker
Board thickness divided by hole diameter decides whether a hole is routine, expensive, or a conversation with your fabricator.
How this is calculated
Aspect ratio is board thickness / finished hole diameter for a through hole, and via depth / via diameter for a blind or buried via. Electroplating chemistry has to circulate down the barrel, and it gets harder to keep copper thickness uniform as the hole gets deeper and narrower.
Working guidance for a standard shop: up to 8:1 is routine, 8:1 to 10:1 is available almost everywhere at normal pricing, 10:1 to 12:1 needs a capable fabricator and costs more, and beyond 12:1 you are into specialist processes. Laser blind vias run to a different rule entirely, usually 0.75:1 to 1:1, which is why HDI boards use stacked or staggered microvias instead of one deep hole.
Enter your measured drill diameter and board/layer thickness. If the result exceeds 10:1 for mechanical drilling or 1:1 for a single laser microvia, flag it — the original board may have used a specialized plating process (e.g., conformal or button plating) that your fab house needs to replicate.
HDI Stackup Complexity — A Comparison
| Parameter | Standard Multilayer (8L) | HDI 1+6+1 | HDI 2+4+2 | HDI 3+2+3 (Any-Layer) |
|---|---|---|---|---|
| Lamination Cycles | 1 | 2 | 3 | 4 |
| Via Types | Through-hole only | Through + blind µvia | Through + blind + buried µvia | Stacked µvia (all layers) |
| Typical Min Trace/Space | 4/4 mil (100/100 µm) | 3/3 mil (75/75 µm) | 2.5/2.5 mil (63/63 µm) | 2/2 mil (50/50 µm) |
| Microvia Drill Ø | N/A | 100–150 µm | 75–125 µm | 75–100 µm |
| Reverse-Engineering Difficulty | Moderate | High | Very High | Extreme |
| Typical Copy Turnaround | 7–10 days | 12–15 days | 15–20 days | 20–30 days |
Any-layer HDI (3+N+3 and above) is the most demanding category. Every copper layer connects to every other through stacked filled microvias, which means a single misregistered via pad cascades into failures across the entire board. Our engineers budget additional cross-section verification time for these structures.
Common Failure Points in HDI PCB Copy Projects
Incorrect Dielectric Thickness
Buildup layers in HDI boards often use different prepreg or resin-coated copper (RCC) than core layers. Measuring them as identical — a common shortcut — throws off impedance by 8–15%. We measure each dielectric layer independently.
Via Fill Misidentification
Some HDI boards use conductive-fill microvias; others use non-conductive fill with a copper cap. The two look similar in cross-section but behave differently electrically and thermally. We test conductivity at each via fill to distinguish them.
Material Substitution Errors
The original board may use a low-Dk buildup material (Dk ≈ 3.2) while a clone fabricator defaults to standard FR-4 buildup (Dk ≈ 3.8–4.2). On a 10 GHz signal path, that substitution shifts impedance by ~12%. We specify material Dk/Df in the fabrication notes, not just “FR-4.” For boards operating above 6 GHz, we often recommend pairing the HDI copy with high-frequency laminate cloning techniques to preserve signal integrity.
Where HDI Overlaps with Other Board Types
HDI is a construction method, not a single application. The boards we reverse-engineer span multiple domains:
- High-speed digital: Server, networking, and FPGA carrier boards where HDI enables short, impedance-matched interconnects. These share challenges with high-speed PCB copy projects — skew matching, loss budgets, and via stub management.
- Compact consumer and medical devices: Smartphones, wearables, and implantable electronics use HDI to shrink board area. Flex-rigid HDI hybrids add another dimension — literally — and overlap with flexible PCB copy workflows that handle polyimide buildup layers.
- Dense mixed-technology assemblies: Boards combining fine-pitch BGAs, QFNs, and through-hole connectors on a single HDI substrate are common in industrial controls. These projects benefit from mixed-technology PCB copy experience alongside HDI-specific techniques.
Deliverables You Receive
- Full Gerber file set (RS-274X) — every copper, solder mask, silkscreen, and drill layer
- Stackup drawing with measured dielectric thicknesses, material callouts, and Dk/Df values
- Bill of materials with manufacturer part numbers, alternates where applicable, and placement coordinates
- Pick-and-place centroid file
- Impedance simulation report for all controlled-impedance nets
- Cross-section photographs documenting via structures and layer registration
All files are delivered in formats compatible with Altium, KiCad, and standard Gerber viewers. If you need an overview of high-density PCB copy capabilities before submitting your board, start there for context on our process and equipment.
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Frequently Asked Questions
How many sample boards do you need for an HDI PCB copy?
We typically need two to three identical samples. One is consumed during sequential delamination. The second serves as a reference for component mapping and impedance measurement. A third is useful for any-layer HDI (3+N+3) where additional cross-sections are required to verify stacked microvia registration across all layers.
Can you copy an HDI board if it uses embedded components?
Yes, but embedded passives or ICs add complexity. We X-ray to identify embedded parts, then delaminate carefully to avoid damaging them. Embedded capacitors and resistors are measured for value and tolerance. Turnaround adds 3–5 working days for boards with embedded components compared to standard HDI.
What is the smallest microvia you can accurately reverse-engineer?
We reliably capture laser-drilled microvias down to 75 µm (approximately 3 mil) diameter. Below that — some advanced packaging substrates use 50 µm vias — we can still image and document them, but fabrication of the clone may require a specialized substrate fab rather than a standard HDI shop.
How do you handle impedance matching on an HDI copy?
We measure dielectric thickness per layer, identify the laminate material (or its closest equivalent), and run 2D field-solver simulations for every controlled-impedance net. Trace widths in the Gerber output are adjusted if needed so that the clone meets the original impedance targets within ±5% at the specified fabrication stackup.
Is HDI PCB copy more expensive than standard multilayer cloning?
Yes. The additional lamination cycles, microvia mapping, and cross-section work increase engineering time significantly. A standard 8-layer copy might start around $800–$1,200 for the engineering package, while an equivalent 8-layer HDI (1+6+1) typically starts at $1,500–$2,500 depending on via complexity and board size. Any-layer designs cost more.
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