HDI PCB Copy: Where the Hard Parts Actually Are

An HDI PCB copy is possible, but it isn’t the same job as copying a regular multilayer board. The difficulty isn’t the traces — it’s the vias. Stacked and staggered microvias, buried cores from sequential lamination, and via-in-pad under a 0.4 mm BGA mean the connectivity lives inside the laminate where no camera can see it. Getting that right is the whole project.

If you’re holding a dense six- or ten-layer board with laser-drilled microvias and no design files, this page tells you how the work actually runs, what makes a given board easy or hard, and what to send us for a straight feasibility answer.

What makes an HDI board different from a regular multilayer copy

On a conventional through-hole multilayer board, every via goes from top to bottom. Once you’ve imaged the layers, the vias are easy — you drill the same hole in the same place and connectivity falls out of the geometry.

HDI throws that away. An HDI stackup is built up in stages: a laminated core, then dielectric and copper added on each side, with laser-drilled microvias connecting only adjacent layer pairs. A 1+N+1 board has one build-up layer per side. A 2+N+2 has two, and those microvias may be stacked directly on top of each other or staggered sideways by a few mils. Add buried vias inside the core and blind vias from the outer layers, and a single net can hop layers three times in a 2 mm span.

So the copy job has two halves that must agree with each other:

• Layer artwork — the copper geometry on each of the N layers, recovered by imaging and layer separation.
• Via architecture — which via type connects which layer pair, at what diameter, capture pad size, and in what sequence the panel was laminated.

Get the artwork perfect and the via structure wrong, and the fabricated board is electrically dead. That’s why HDI work costs more and takes longer than an equivalent layer count in a conventional stackup.

How we actually reverse engineer an HDI stackup

Before anything is destroyed

The board gets fully documented while it’s intact. High-resolution scans of both sides, oblique lighting to pull silkscreen out of dark solder mask, and a component inventory with every marking recorded — including the ones under shields and heatsinks. Cross-sectional thickness is measured with a micrometer at several points, because total thickness plus layer count constrains what dielectric thicknesses are plausible.

Then X-ray. On HDI boards, X-ray is not optional. Transmission imaging shows buried via locations, plated hole patterns under BGAs, and internal plane cutouts before a single layer is removed. It also tells us where the interesting complexity is concentrated, so we know where to slow down.

Cross-sections tell us the stackup

We cut coupons from areas with representative via structures — a BGA field, a connector region, a spot with a dense via cluster — pot them, polish them, and look at the cross-section under a microscope. That single step answers questions nothing else can:

• How many build-up layers, and whether microvias are stacked or staggered
• Microvia diameter, target pad diameter, and aspect ratio
• Which layers the buried vias span, which reveals the lamination sequence
• Dielectric thickness per layer and copper weight per layer
• Whether microvias are copper-filled, resin-filled with a copper cap, or plated only

Copper weight matters more than people expect. A 0.5 oz build-up layer and a 1 oz core layer etch differently and carry different current, and IPC-2152 sizing only makes sense once you know which is which.

Layer separation and imaging

From there it’s controlled removal, layer by layer, scanning each copper layer before moving down. Alignment is held with fiducials referenced to plated features that persist across layers. The scans get vectorized and cleaned by an engineer, not left to an autotracer, because a 3 mil trace next to a 3 mil gap under a slightly over-etched edge is a judgment call the software gets wrong.

The output is a full layer set plus a drill and via map that distinguishes through vias, blind vias, buried vias, and each level of microvia. If you want to see the format the layer stack comes back in, our page on what arrives at handover lists the file set in detail.

Verification against the original

Netlist comparison is the check that matters. We extract connectivity from the recovered layer set and compare it net by net against continuity measurements taken on the original board before teardown, plus continuity probed on a second sample if you send one. Discrepancies get resolved by going back to the cross-sections or the X-ray images, not by guessing.

Fabricated first articles are then inspected against IPC-A-600 for acceptability and IPC-6012 class expectations for the board type, with particular attention to microvia target pad connection quality — that’s the classic HDI failure mode, and it usually shows up as a cracked microvia interface after thermal cycling rather than as an open on day one.

Which HDI boards are harder, and which we sometimes decline

Honest version: feasibility varies a lot, and layer count alone doesn’t predict it.

A few things that change the answer for the worse: conformal coating or potting over the whole assembly, unmarked or house-numbered ICs with no datasheet path, and RF sections where the copy has to hit an impedance target we can only infer from geometry and a dielectric constant we have to estimate. That last one overlaps heavily with signal-integrity-critical board duplication, and it’s worth flagging early if your board has controlled-impedance differential pairs above a couple of gigahertz.

We’d rather tell you a board is a poor candidate at the quote stage than take the job and hand you a stackup we’re not confident in.

What to send us, and what comes back

Feasibility on HDI is a real assessment, not a form response. To give you one, send:

1. Clear photos of both sides on a dark, non-reflective background, whole board in frame, in focus, with no glare across the solder mask.
2. Board dimensions and overall thickness, plus your best guess at layer count if you have one.
3. Close-ups of the main ICs so we can read the markings — the MCU, any FPGA or CPLD, memory, and power controllers.
4. One line on deliverables: Gerbers only, Gerbers plus BOM, full schematic, or working assembled boards.
5. Quantity and intent: one-off repair, spares stock, or a production run. It changes what’s worth documenting.

What comes back from us: a feasibility read with the specific risks named, an estimated lead time, a price, and how many physical samples we need. On HDI we usually ask for two boards — one for destructive cross-sectioning and layer separation, one kept intact as the electrical reference. One board is workable but narrows the margin for error.

Cost drivers on HDI, so quotes stop feeling arbitrary: layer count and build-up depth, board area, component count and how many are fine-pitch BGAs, whether controlled impedance has to be matched, the number of cross-section coupons the via architecture demands, and whether firmware from an onboard microcontroller is part of the scope. If the answer to that last one is yes, that’s a separate workstream with its own feasibility question. Firmware recovery is only appropriate where you hold the rights to the code — recovering your own lost binary, or maintaining equipment you own — and everything we do runs under NDA with the customer responsible for the underlying IP position.

When redesign beats copying

Sometimes the right answer isn’t a copy at all. If the original board uses a controller that went end-of-life, or if the HDI stackup was chosen for a package that now has a coarser-pitch equivalent, reproducing the old geometry locks you into a build that’s expensive forever.

Cases where redesign usually wins:

• The board exists only to fan out one obsolete BGA, and a current part in a QFN would let you drop to a conventional 4-layer stackup.
• You need thousands of units and the HDI premium compounds.
• Multiple components on the BOM are unobtainable, so you’re changing the design anyway.

Cases where a faithful copy wins: qualified equipment where any change triggers requalification, boards where the mechanical footprint is fixed by the enclosure, and situations where you need drop-in spares next month. Boards built on high-Tg laminate for elevated operating temperatures also tend to argue for a faithful copy, since the thermal qualification is already behind you.

FAQ

Can you copy an HDI board with stacked microvias?

Usually yes. Stacked microvias are identified by cross-sectioning coupons through representative via clus

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