High density PCB reverse engineering is priced off four things: layer count, board area, component count, and how much of the routing is buried under BGAs or in microvia stackups. A dense six-layer control board the size of a credit card can cost more than a sparse ten-layer board twice its size. Lead time follows the same logic — expect days for a simple board and a few weeks for a fine-pitch, high-layer-count assembly. Below is what actually drives each number.
What counts as “high density,” and why it changes the price
Density is not the same as layer count. A board becomes a high-density job when the routing pitch drops far enough that copper features start crowding each other: 3 mil traces and gaps, via-in-pad, staggered or stacked microvias, 0.4 mm pitch BGAs, 0201 and 01005 passives packed shoulder to shoulder.
Every one of those features costs engineering hours, and for concrete reasons:
- Fine trace and gap. At 3 mil pitch, the scanning and image-registration work has to be much tighter. Small alignment errors between layers that would be harmless on a 10 mil board create false nets on a dense one, so every questionable connection gets checked twice.
- BGA and LGA packages. The pads are invisible from outside. Nets under a 484-ball BGA have to be recovered from the inner layers and cross-checked, usually with X-ray first and then with layer-by-layer imaging.
- Via-in-pad and buried vias. You can’t probe them. Determining which layer pair a buried via actually connects is a separate step, not a bonus.
- Tiny passives. A 01005 resistor has no legible marking. Value comes from in-circuit measurement plus circuit context, and there are hundreds of them.
- Ground and power plane fragmentation. Dense boards split planes into many islands. Getting the stitching and the split boundaries right matters for signal integrity, and it takes deliberate tracing rather than a quick flood fill.
That’s the honest reason two “six-layer boards” can differ by a factor of three in price. The layer count is on the quote form; the density is what we look at in your photos.
How we price a high density board
We quote per board, not per hour, but the internal math is hours. The main multipliers:
| Factor | Effect on cost and time |
|---|---|
| Layer count (4 → 8 → 12+) | Roughly linear on imaging time, worse than linear on net verification, since every added plane adds cross-checking |
| Unique component count | Drives BOM and identification hours more than total placement count does |
| Fine-pitch BGA / LGA count | The single biggest step change. One 0.5 mm BGA is manageable; four of them changes the schedule |
| Microvia / buried via stackup | Adds a dedicated stackup determination phase before net extraction starts |
| Deliverable set | Gerber and drill only is the cheapest. Add netlist, then schematic, then a full editable CAD database — each tier adds real work |
| Sample condition | A working board you allow us to consume is cheapest. A single non-destructible board is the most expensive path |
| Firmware involved | Priced separately. MCU code readout is a different discipline from copper tracing |
We don’t publish a fixed price list for dense boards because a number would be meaningless without seeing the board. What we will do is look at your photos and come back with a firm figure, not a range that widens later. If you want to see how the same logic scales with laminate choice, the notes on high Tg board reverse engineering cover the material side of the same problem.
Where you can genuinely save money
Send two or three identical boards. If we can sacrifice one to layer separation and keep another intact for electrical verification, the job goes faster and the price drops. Also, tell us what you actually need. Plenty of customers ask for a full schematic when what they really need is a manufacturable Gerber set to build spares — that’s a meaningfully cheaper deliverable.
What the lead time really depends on
Ranges we see in practice, assuming samples are in hand and no waiting on your side:
- 4-layer dense board, moderate component count, Gerber + BOM: a handful of working days.
- 6 to 8 layers with one or two fine-pitch BGAs, full schematic: a couple of weeks is realistic.
- 10+ layers with stacked microvias and multiple BGAs, schematic plus editable CAD: several weeks, and we’ll give you interim milestones rather than one delivery date.
Two things stretch a schedule more than anything else. First, single-sample jobs — no destructive work means slower, more careful methods. Second, ambiguous components: a laser-marked SOT-23 with a two-character code, or a house-numbered ASIC. Those turn into research tasks, and research doesn’t respect a schedule.
Rush handling exists and it is real work reordering, not a surcharge for nothing. If you have a line down, say so in your first message. That’s the whole reason our PCB reverse engineering service keeps capacity open for urgent repair jobs.
The process, in the order it actually happens
- Intake and imaging. High-resolution scans of both sides at known scale, plus dimensional measurement of board outline, mounting holes, and connector positions. Board thickness by micrometer.
- X-ray. Before anything is taken apart. This is where we find buried vias, count inner layers, see BGA ball patterns, and spot internal plane structure. On dense boards this step decides the plan for everything after it.
- Component identification. Marking capture under a stereo microscope, cross-referenced against manufacturer marking codes. Passives get in-circuit or removed-and-measured values. Anything unreadable is flagged, not guessed.
- Desoldering and layer separation. Components come off, the board is delaminated layer by layer, and each copper layer is imaged individually. This is the only reliable way to get inner-layer routing on a board with via-in-pad.
- Layer registration and copper extraction. Each layer image is aligned to a common datum using drilled features, then copper is vectorized. Registration accuracy here is what separates a usable file from a board that fails at fab.
- Netlist build and verification. The extracted netlist is compared against continuity measurements taken on an intact sample before teardown. Discrepancies get resolved individually — a mismatch is treated as a real finding, not noise.
- Deliverable generation. Gerber, drill files, stackup with dielectric thicknesses and copper weights, BOM, netlist, and — if ordered — schematic and CAD project.
- Design rule and acceptability review. Output is checked against IPC-2221/IPC-2222 general design rules and, where relevant, IPC-2152 for conductor current capacity. If you’re taking the files to a fab, an IPC-6012 class 2 or class 3 target should be stated up front, because it affects annular ring and plating expectations in the output.
On multi-BGA boards, step 6 is where most of the schedule goes. Extracting copper is mechanical. Proving the netlist is correct is judgment.
What to send us, and what comes back
To get a firm quote on a high density board, send:
- Clear photos of both sides on a dark background, entire board in frame, no glare, focused enough that you can read the large IC markings.
- One or two close-ups of the densest area and of any BGA or QFN cluster.
- Board dimensions in mm, plus board thickness if you know it.
- Layer count if you know it. If you don’t, say so — we’ll estimate from the photos and confirm by X-ray.
- The main chip markings typed out as text, exactly as printed, including the line breaks.
- One line on deliverables: Gerber only, Gerber + BOM, full schematic, or editable CAD.
- Whether firmware recovery is needed, and how many sample boards you can send.
What comes back within a working day or so: a feasibility assessment, a lead time, a price, and a note on anything we consider risky. If we think a specific component or a section of the board is going to be a problem, you hear it in that first reply, not after you’ve paid.
The limits worth knowing before you order
Not every dense board comes back complete. The cases that give us trouble:
Potted and conformally coated assemblies. Hard epoxy potting over a fine-pitch region can damage traces on removal. Sometimes recoverable, sometimes not — we’ll tell you the odds after seeing photos, not before.
House-numbered and custom silicon. If a critical part is marked with a customer part number and nothing else, we can recover its footprint, its pinout in-circuit, and its net connections. We cannot tell you what to buy to replace it. That’s a sourcing problem, and we’ll say so plainly.
Damaged or partially burned boards. A charred region on a dense board can destroy the copper we need. A second sample, even a non-working one, often rescues the job.
Sequential-lamination HDI with stacked microvias. Recoverable, but the stackup determination is slower and the reproduction cost at the fab goes up. Worth knowing before you commit to duplicating rather than redesigning.
Locked microcontrollers. Copper tracing tells you nothing about firmware. Whether the code can be read depends on the specific part and its protection state — STM32 RDP level, an MSP430 JTAG fuse, AVR lock bits — and feasibility is decided per device, never assumed. We quote firmware work separately and describe the honest probability for that part number.
On the legal side: we ask that you hold the rights to the design or have a legitimate maintenance, repair, obsolescence, or failure-analysis reason for the work, and every project runs under NDA. Recov
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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