A high density PCB copy is the same basic job as any board duplication — recover the layout, the netlist, and the bill of materials from a physical sample — but the density changes which steps dominate the schedule. On a dense board, the hard parts are layer separation without losing 3 mil traces, tracing nets that disappear under a 0.4 mm pitch BGA, and confirming via structures you cannot see from either surface. Everything else is routine.
This page is written for the engineer or product owner who already has the board in hand and wants to know what they’re signing up for.
What makes a board “high density” in copy terms
Density in a fab sense means fine lines, tight spacing, small drills, and thin dielectrics. Density in a reverse engineering sense means something slightly different: how much information is hidden from direct observation.
A 6-layer board with 5 mil traces and plated through holes everywhere is dense to build and easy to read, because every via punches through the whole stack and gives you a visible reference point on both outer layers. A 8-layer board with staggered microvias, buried vias between layers 3 and 6, and BGAs on both sides is far harder to read even if the trace widths are identical. The vias no longer tell you where nets go.
So when we scope a high density PCB copy, we’re really asking four questions:
- Minimum feature size. Line width, spacing, and annular ring. Once traces drop toward 3 mil, imaging resolution and registration between layers start to matter more than operator time.
- Via architecture. Through-hole only, or blind and buried, or a stacked microvia HDI build. This single answer changes the price more than layer count does.
- Component pitch and package type. Fine-pitch BGA, LGA, QFN with a thermal pad, 0201 passives, chip-scale packages. Anything whose pads you cannot probe with a needle adds work.
- Dielectric thickness and material. Thin cores and high-Tg or low-loss laminates behave differently under controlled delamination.
How we actually read a dense multilayer board
The sequence is not mysterious, but the order matters and the checkpoints are where accuracy comes from.
Before anything destructive
The board gets photographed and scanned on both sides at high resolution first, while it’s still assembled and functional-looking. Then we do component identification from markings, packages, and measured values — every marking that’s legible gets logged, and unmarked parts get measured in-circuit or after removal. We X-ray the board before disassembly, which on dense builds is the only way to see buried via columns, BGA ball count and pattern, and internal plane cutouts before we start grinding.
Layer separation and imaging
Components come off with controlled hot air or IR reflow, pad geometry preserved. Then the stack gets separated layer by layer — abrasive removal on the outer copper, then dielectric removal down to the next copper layer, scanning after each pass. On a thin dielectric with 3 mil traces, this is the step that can go wrong: remove 15 microns too much and you lose the thinnest features on the layer below.
Registration is handled with physical fiducials — through holes and board edges — so every scanned layer lines up in the same coordinate system. If the board has no through holes at all, which happens on some HDI designs, we drill our own reference holes in unused board area before separation.
Rebuild and verify
The scans get vectorized into copper layers, drills are placed by size and position, and the stackup is reassembled with the measured dielectric thicknesses. Then comes the part that separates a real job from a fast one: the rebuilt netlist gets checked against the physical board. Continuity between accessible test points, connector pins, and component pads is measured and compared to what the reconstructed layout claims. Discrepancies get chased down individually, and on a dense board there are always a few in the first pass.
Impedance-sensitive nets get treated separately. On a dense board carrying DDR, high-speed serial, or RF, the trace geometry and reference plane spacing are part of the function, not decoration — the same discipline used for a high speed board duplication applies here. We record measured widths and dielectric heights rather than snapping them to a round number.
Which parts of a dense board are genuinely hard
| Feature | Why it slows things down | How we handle it |
|---|---|---|
| 0.4–0.5 mm pitch BGA | Escape routing hides under the package; dog-bone vias and via-in-pad are hard to distinguish optically | X-ray before removal, plus per-ball continuity checks after the package is off |
| Stacked or staggered microvias | No visible signature on either outer surface; a net can hop three layers with no through hole | Cross-section sampling in a sacrificial area, confirmed against X-ray |
| 3 mil traces on thin dielectric | Small over-grind destroys features permanently | Slower material removal, scan after every pass, second sample if available |
| Solid planes with fine anti-pads | Plane splits and stitching decide the return path; easy to redraw wrong | Plane layers vectorized as geometry, not as generic pours |
| Conformal coating or potting | Blocks optical inspection and probing | Chemical or mechanical removal on a test area first, to confirm the process doesn’t lift copper |
| Unmarked or laser-scrubbed ICs | Part identity is a guess until it’s proven | Pinout behavior, package, supply rails, and family narrowing; flagged as unconfirmed if not provable |
What we need from you, and what you get back
For a first-pass feasibility answer on a high density board, send this — it takes five minutes and saves a week of back and forth:
- Photos of both sides, whole board in frame, laid on a dark matte background, sharp and evenly lit. Add close-ups of any BGA area and any connector field.
- Board dimensions and overall thickness, plus layer count if you know it.
- The marking on the main chip — the MCU, FPGA, or SoC — typed out exactly as printed, including the date code line.
- One line on deliverables: Gerbers only, or Gerbers plus BOM, or full schematic and netlist, or a working board built and tested.
- Whether the board still powers up. A working sample lets us verify the rebuild functionally; a dead one limits us to continuity checks.
What comes back is a feasibility assessment naming the specific risk areas on your board, a lead time, and a price. When you approve, the output set typically includes layer-by-layer Gerbers, drill files with via type called out, a stackup sheet with measured dielectrics, a BOM with reference designators, and a netlist — with schematic capture and a full handover file package as separate line items rather than assumed.
Cost drivers on dense work are layer count, board area, via architecture, component count, number of BGAs, and whether firmware is involved. Two boards with the same layer count can differ substantially in price if one is HDI and the other is not.
The honest limits
Dense boards are where a copy service should tell you what it can’t promise.
One sample is a real constraint. Layer separation is destructive. With a single board and 3 mil features, a bad pass on layer 4 leaves us reconstructing from partial data. Two or three samples make a dense job meaningfully more reliable and often cheaper per net.
Damaged or previously reworked boards. Lifted pads, burned traces, and hand-soldered rework hide the original intent. We can usually reconstruct from surrounding geometry, but we’ll flag guesses as guesses.
Unmarked custom silicon. An ASIC, a customer-marked MCU, or a security element with no public part number can be characterized behaviorally, but we won’t claim to identify it if we can’t. Sometimes the right answer is that a functional clone isn’t achievable and a partial recovery on a laminate-specific build plus a redesign around a current part is the better path.
Embedded passives and embedded components. Resistors or capacitors buried inside the stack are recoverable in principle from cross-sections but add cost, and tolerance recovery is approximate.
Firmware is a separate question. Copying the copper doesn’t get you the code. If the design relies on a programmed MCU and you no longer have the hex file, that’s a distinct piece of work with its own feasibility depending on the part and its protection state — RDP level on an STM32, lock bits on an AVR or 8051, JTAG fuse or BSL password on an MSP430. Some configurations are practical, some are not, and we say which before quoting.
On the legal side: we work on the assumption that you hold the rights to the design or are authorized to have it recovered — maintenance of your own equipment, obsolescence migration, failure analysis, recovering documentation you paid for and lost. Compliance with applicable IP law is yours to hold; every project runs under NDA on our end.
Frequently asked questions
Can you copy a dense HDI board if you only have one sample?
Often yes, but with more risk and a longer schedule. Layer separation destroys the sample, so any imaging error on a thin dielectric can’t be redone. We’ll X-ray and cross-section a sacrificial edge first to characterize the stackup before committing. If you can supply a second board, even a non-working one, the reliability of the reconstruction improves noticeably.
How long does a high density PCB copy take compared to a simple board?
Meaningfully longer. A two-layer board with through-hole parts is a short job. A dense multilayer board with fine-pitch BGAs and buried vias takes multiples of that, because inner layers are imaged one at a time and the netlist verification pass is much larger. Board area and BGA count drive the number more than layer count alone. We quote a specific window after seeing your
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