High speed PCB reverse engineering costs more and takes longer than an ordinary board for one reason: on a board carrying DDR, PCIe, SerDes or gigabit Ethernet, the copper geometry is the design. Trace width, dielectric thickness, differential spacing and length matching all have to be measured and reproduced, not just traced. Expect a multi-week job on a dense multilayer board, and expect the quote to hinge on layer count, BGA pitch, and whether you need controlled impedance verified.
Why a high speed board isn’t just a denser board
On a 5 V logic board, if you get a trace 20% narrower than the original, nothing happens. On a 6 Gbps differential pair, a 20% width error moves the impedance out of spec and the link either degrades or refuses to train. That’s the whole cost story in one sentence.
So high speed PCB reverse engineering adds work that a general-purpose board copy never touches:
- Dielectric measurement. Cross-sections through the board to get actual copper thicknesses and prepreg/core thicknesses layer by layer, because the stackup determines impedance and the fab notes are gone.
- Material identification. Whether the laminate is standard FR-4, a mid-loss material, or a low-Dk/low-Df PTFE or hydrocarbon system changes both the impedance math and the board price. We infer this from cross-section appearance, glass weave, board markings, and where the design sits in frequency.
- Differential pair extraction. Pairs have to be identified as pairs, kept as pairs in the netlist, and carry their intra-pair skew and inter-pair matching into the layout file. A generic net-by-net trace loses that.
- Length matching and topology. DDR address/command groups, byte lanes, and clock nets have deliberate serpentine and via-count choices. Those get recorded as constraints, not accidents.
- Return path and reference planes. Which plane each high speed layer references, where the plane splits are, and where stitching vias sit.
That’s engineering hours, and hours are what you’re paying for.
What actually drives the price
We don’t publish a number because a “high speed board” ranges from a four-layer gigabit Ethernet switch card to a sixteen-layer FPGA carrier with buried vias. Here’s what moves the quote, roughly in order of impact.
Layer count and via structure
Layer count is the biggest single driver, because inner layers have to be exposed and imaged one at a time. Blind and buried vias make it worse — the layer pairs have to be correlated so a via that connects L3–L6 doesn’t get drawn as a through-hole. HDI with stacked microvias is the hardest case in this category, and it’s where multilayer board recovery work takes the longest.
BGA pitch and count
A 0.8 mm pitch BGA is manageable. A 0.5 mm or 0.4 mm pitch part with 900+ balls and dog-bone escapes into three routing layers is a different animal. Every ball has to be mapped to a net, and X-ray imaging plus careful layer alignment is the only way to do it reliably.
Whether you need impedance verified
There’s a real fork here. Recovering the geometry is one job; confirming that the reproduced stackup hits the original target impedance is another. The second involves TDR measurement on the original board where a suitable structure exists, plus a field-solver calculation against the measured stackup. It adds days. It’s also the difference between a file set that works and one that looks right.
Component identification
High speed boards are full of parts that don’t help you: laser-marked passives, house-numbered clock generators, custom-programmed CPLDs, and 0201 or 01005 passives that have no marking at all. Values on the small passives get measured; equalizers, redrivers and PHYs get identified from package, pin behavior, and context. Anything laser-marked with a customer part number takes research time and sometimes ends in a functional equivalent rather than an exact match.
Deliverable set
Gerbers plus drill is the cheapest outcome. Add a netlist, then a full schematic with hierarchy and net naming, then a native CAD layout with impedance constraints and design rules, and each step adds hours. Firmware or programmable logic contents, if any, are priced separately.
How the cost tiers compare
| Board class | Typical effort | What dominates the schedule |
|---|---|---|
| 4-layer, single gigabit link, largest part is a QFP | Lowest in this category | Layer imaging; one differential group to characterize |
| 6–8 layer, DDR3 plus Ethernet, 0.8 mm BGA | Moderate | Byte-lane grouping, length matching, plane referencing |
| 10–16 layer, SerDes above 5 Gbps, fine-pitch BGA | High | Cross-sectioning, via structure mapping, impedance verification |
| HDI with stacked microvias, mixed dielectric | Highest | Microvia correlation, material identification, X-ray dependency |
How long a high speed board really takes
Lead time tracks layer count and BGA density much more closely than board size. A four-layer high speed board with a handful of controlled-impedance nets is usually a matter of days. A dense multilayer board with fine-pitch BGAs is measured in weeks, and if the stackup has to be cross-sectioned and impedance-verified, add more.
The sequence, in the order it actually happens:
- Intake and inspection. Photograph both sides, log every component, note damage, note anything potted or shielded.
- X-ray. Internal via structure, BGA ball integrity, and a first look at buried features before anything destructive.
- Cross-section. A coupon area of the board is sectioned and polished to measure copper weights and dielectric thicknesses. This is the step that makes impedance work possible.
- Component removal and layer separation. Parts come off, and inner layers are exposed and scanned in registration so vias line up across layers.
- Net extraction. Copper is vectorized, vias are correlated, and the netlist is built. Differential pairs are tagged as pairs at this stage, not later.
- Schematic and layout rebuild. Nets become a readable schematic; geometry becomes a CAD layout with the stackup and impedance rules entered as constraints.
- Verification. The rebuilt netlist is checked back against the physical board point to point. Where the customer needs it, a bare-board prototype is fabricated and TDR-checked against the original.
Verification is the step people try to cut to save time. On high speed work it’s the step you least want to cut, because a netlist error on a DDR data line looks fine on the screen and fails on the bench. Related sector pages — telecom board recovery and instrumentation board work — follow the same flow with different verification emphasis.
What to send us for a quote
We can quote most high speed boards from photos and a few lines of text. Send:
- Clear photos of both sides, whole board in frame, on a dark background, in focus. Add close-ups of the largest BGAs and any connector fields.
- Board dimensions and overall thickness if you have a caliper handy. Thickness plus layer count tells us a lot about the stackup.
- Layer count if you know it, or the edge of the board photographed under light so we can count plating rings.
- The markings on the main chips — the SoC, FPGA, PHY, memory, clock generator. Type them out; laser marking rarely photographs well.
- What the board does and how fast. “DDR3-1600 and two 10G SFP cages” tells us more than a page of description.
- One line on which deliverables you need: Gerbers only, Gerbers plus BOM, full schematic, native CAD with impedance constraints, or a working prototype.
What comes back is a feasibility assessment (including anything we think is risky), a lead time, and a price. If the photos leave a real question open, we’ll say what we need instead of guessing at a number.
The honest limits
Some cases are harder, and a few sometimes aren’t feasible as an exact reproduction:
- Stacked-microvia HDI where two or three build-up layers must be correlated with sub-100 µm accuracy. Doable, but slow, and it usually needs more than one sample board.
- Exotic laminate. We can identify the dielectric class and measure thicknesses, but naming the exact commercial material with certainty isn’t always possible. When it isn’t, we specify by measured Dk/Df target and thickness so a fab can match it — which is usually what you actually need. Materials with high glass transition temperatures behave differently under sectioning; that’s covered in more detail on our high Tg board reverse engineering page.
- Custom and house-marked silicon. An ASIC or a house-numbered clock buffer may have no public datasheet. We can pin out its behavior in-circuit, but we can’t manufacture a replacement for it.
- Programmed logic. A CPLD or FPGA configuration is a separate question from the copper. Feasibility depends entirely on the specific device family and its security settings, and it is quoted on its own.
- Single damaged sample. If the only board you have is burned or delaminated in a region that carries high speed routing, some nets may be unrecoverable from that sample. Two boards — one to keep intact, one to consume — is always the better position.
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