High Speed PCB Copy: Where the Hard Parts Actually Are

A high speed PCB copy is only useful if the copied board keeps the same electrical behavior, not just the same picture of the copper. That means the dielectric thicknesses, trace widths, spacing, reference planes, and via structures all have to be recovered as measured values — because on a board running DDR3, gigabit Ethernet, PCIe, LVDS, or a fast ADC bus, those dimensions are the design. Get the stackup wrong by a few mils and the board still assembles, still powers up, and still fails timing.

So the honest version of this service is less about tracing nets and more about metrology. Here’s what that looks like in practice.

What actually has to be measured, in what order

The net-level copy of a high speed board is the easy part. Any competent lab can peel layers and reproduce connectivity. The work that decides whether the clone performs is the physical stack.

1. Stackup and dielectric

We cross-section the board — usually in a low-value corner or a coupon area — and measure each dielectric thickness, each copper thickness, and the prepreg-to-core arrangement under a calibrated microscope. Copper is measured after etch, so 1 oz nominal often comes back at something other than 1.4 mil. Those numbers feed the impedance model. Guessing “standard 4-layer 1.6 mm” on a controlled-impedance board is the most common way a copy goes wrong.

2. Dielectric constant, as far as it can be determined

This is where honesty matters. Dk isn’t printed on the board. We identify the laminate class from cross-section appearance, glass weave style, resin content, board markings, and sometimes a TDR measurement on a known trace to back out an effective Dk. If the original used a specific low-loss material — Rogers, Megtron, Tachyon — the weave and color usually give it away, and the trace geometry has to be re-solved if you plan to build on a substitute. High-Tg FR-4 boards get their own treatment; if that’s what you have, the notes on copying high-Tg laminate boards apply to the material side of the job.

3. Trace and pair geometry

Line width, edge-to-edge spacing within differential pairs, and clearance to reference copper get measured on the imaged layers, not scaled off a photo. We record intra-pair spacing separately from pair-to-pair spacing, because those two numbers tell us the target differential impedance and the coupling strategy the original designer used.

4. Length matching and topology

Serpentines are the designer leaving you a note. Where a bus has deliberate meanders, we measure the electrical length of every member of that group and record the matching tolerance, then carry it forward as a constraint rather than as artwork. Same for T-branches, fly-by DDR routing, and where the termination sits relative to the receiver.

5. Via structures and stubs

Drill diameter, pad and antipad diameter, whether the via is through, blind, or buried, and whether any are backdrilled. Backdrilling is easy to miss and very visible at 10 Gbps. X-ray and cross-section both get used here; on dense boards we lean on the workflow described for high density board duplication, since the via and layer-transition problems overlap heavily.

6. Reference plane integrity

We map every plane split, every void, and every stitching via near a high speed net. A trace that crosses a plane split has a return path problem the original designer either solved or lived with. Either way, the copy has to reproduce the same decision — silently “cleaning up” a split is a change, not an improvement.

Why high speed PCB copy costs and takes more than a plain multilayer job

Two boards can both be six layers and be completely different jobs. The high speed one adds destructive cross-sectioning, impedance modeling, TDR verification, and a documented constraint set that a normal copy never produces.

That last row surprises people. If you send one board and it’s the only one in existence, we can still work, but we lose the ability to cross-section freely and the stackup data becomes partly inferred. Say so up front and we’ll plan around it.

Which high speed boards get difficult, and which sometimes aren’t feasible

No lab should tell you every board is the same. These are the cases that genuinely change the answer:

• Unmarked exotic laminate. If the board uses a low-loss material with no legible marking and no coupon, Dk is an estimate. We’ll say so, model conservatively, and recommend a TDR check on the first article rather than pretend to certainty.
• HDI with stacked microvias. Recoverable, but layer separation is slower and via-in-pad structures need X-ray plus sectioning to resolve. Cost climbs with the number of build-up layers.
• Embedded passives or embedded capacitance layers. Thin-dielectric power-ground pairs and buried resistors can be identified, but sourcing an equivalent material is a procurement question as much as an engineering one.
• Boards with an unreadable or sanded-off marking on a critical high speed part. A PHY or SerDes with a lasered-off top mark may be identifiable by package, pinout, and behavior, or it may not be. This is the single most common blocker.
• Custom silicon, ASICs, or programmed logic. We can copy the board around the part; we cannot conjure the part. If the design depends on an FPGA or CPLD whose configuration lives in a protected device, that’s a separate conversation about whether the contents are recoverable at all.
• Boards where the failure was a design margin problem in the first place. Copying it faithfully copies the marginal timing too. Sometimes the right answer is a layer-count-aware re-layout rather than a straight duplicate.

We’d rather tell you a board is a 70/30 proposition before you ship it than discover it halfway through. Feasibility comes first, always.

What to send us, and what comes back

You can get a real feasibility answer from photos alone. Here’s the short list.

1. Clear photos of both sides on a dark, non-reflective background, whole board in frame, square to the camera, plus close-ups of any connector or IC area you care about. Diffuse light, no flash glare across the solder mask.
2. Board dimensions and overall thickness, measured with calipers if you have them.
3. Layer count if you know it, and the top marking of the main high speed devices — the PHY, the SerDes, the memory, the processor. Type the marking out as text; photos of laser marks are often unreadable.
4. What interfaces run on it and roughly how fast. “DDR3-1600 and two gigabit ports” changes our approach far more than the layer count does.
5. One line on deliverables: do you need Gerbers only, Gerbers plus BOM, a full schematic, or working assembled boards?

What comes back from us: a feasibility assessment naming any specific risks we see, a lead time, a price, and a note on how many sample boards we want. A dense multilayer high speed board with BGAs is meaningfully longer than a simple two-layer job — the inner layers have to be imaged separately and the cross-section work is sequential, not parallel.

On delivery, the file set for a controlled-impedance board should include the fabrication drawing with the measured stackup, an impedance target table by net class, the drill file with via types called out, the BOM with the high speed parts fully specified, and the assembly data. If a quote doesn’t mention a stackup drawing, ask why.

How we verify a high speed clone before you see it

Verification is where a serious high speed PCB copy separates itself. Netlist comparison against the extracted netlist catches connectivity errors. Bare-board electrical test catches opens and shorts. Neither tells you anything about impedance.

So we add an impedance test coupon on the panel and TDR it against the modeled targets. First articles get inspected to IPC-A-600 and IPC-6012 for plating, annular ring, and laminate condition — a barrel crack that passes continuity at DC will still ruin a 5 Gbps link. Where the design allows, we bring up a fully assembled board and run link-level tests: memory training passing, PHY linking at full rate, error counters clean over a soak.

Trace width and copper thickness assumptions get sanity-checked against IPC-2152 for anything carrying real current, and general clearance and geometry decisions stay inside IPC-2221 guidance unless the original deliberately went tighter — in which case we document that it did.

Legitimate use, plainly

The work we take on is maintenance and continuity work: a controller board that’s out of production, a test instrument whose vendor has folded, a design whose original CAD files left with an engineer years ago, obsolescence-driven migration to a current part, or failure analysis on a board that keeps dying in the field. You’re responsible for holding the rights to the design you send, and for compliance with applicable IP law; every project runs under NDA, and sample boards and files stay inside the lab.

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