How a project runs

What Is the PCB Copy Process?

The PCB copy process is a structured reverse-engineering workflow that extracts manufacturable design files—Gerber, drill, BOM, and optionally a schematic—from a physical circuit board. It typically moves through seven stages: board preparation, high-resolution scanning, chemical or mechanical delayering, layer-by-layer CAD tracing, netlist verification, design-rule check, and final file output. A standard 2-layer board takes 3–5 working days; a 10-layer board with BGAs can take 10–15. Accuracy on trace width and spacing routinely reaches ±0.5 mil (0.013 mm) when proper equipment and procedures are used.

Why Understanding the PCB Copy Process Matters

If you are sourcing a board copy for legacy replacement, second-source qualification, or redesign reference, knowing what happens at each stage lets you ask the right questions before committing budget. It also helps you prepare the board correctly—wrong prep is the single largest cause of delays. Our preparation checklist covers exactly what to have ready before shipping.

Understanding the process also sets realistic expectations. A copy is not a photograph—it is a reconstructed engineering dataset. Some information is always inferred rather than measured, and knowing where those inferences happen lets you evaluate quality claims critically.

The 7 Stages of the PCB Copy Process

Stage 1 — Board Intake and Visual Inspection

Every project starts with a physical inspection. Our engineers photograph both sides of the board under controlled lighting, note component markings, measure overall dimensions with digital calipers (±0.02 mm), and record the board thickness with a micrometer. We also check for physical damage—burns, cracked traces, corroded vias—because these affect what can be recovered. In many cases, even a damaged board can still be copied if at least one intact reference layer survives.

At this point the layer count is estimated by examining via structures, edge cross-sections, and board thickness. A 1.6 mm FR-4 board with blind vias almost certainly has 4+ layers. Confirming the exact count matters because it determines the delayering plan.

Stage 2 — Component Removal and BOM Extraction

All components are desoldered—typically with a hot-air station at 300–380 °C depending on solder alloy—and catalogued into a bill of materials. Each part’s package, marking code, manufacturer, and position designator are recorded. For ICs with erased markings, we cross-reference pin count, package, and circuit context to identify the part.

The BOM is delivered as a structured spreadsheet (Excel or CSV) with columns for designator, value, package, manufacturer part number, and substitutes where applicable.

Stage 3 — High-Resolution Optical Scanning

With components removed, the bare board’s top and bottom copper layers are scanned at 2400–4800 DPI using a calibrated flatbed or area-scan camera system. At 4800 DPI, one pixel equals roughly 5.3 µm—enough to resolve 3-mil (0.076 mm) traces and spaces clearly. The scans are stitched, corrected for lens distortion, and aligned to fiducial marks or board edges.

This stage captures the two outermost copper layers in full detail. For a 2-layer board, scanning alone provides the complete copper dataset. For multilayer boards, the inner layers are still hidden under laminate.

Stage 4 — Delayering (Multilayer Boards Only)

Delayering is the most technically demanding step. The board is chemically etched or mechanically milled to expose each inner copper layer one at a time. Chemical etching uses a controlled cupric chloride or ferric chloride bath to strip copper, followed by careful abrasion of the prepreg dielectric to reveal the next layer.

Layer Count	Delayering Method	Typical Duration	Risk Level
2-layer	None required	—	Low
4-layer	Chemical etch + abrasion	0.5–1 day	Low–Medium
6–8 layer	Sequential chemical etch	1–2 days	Medium
10–16 layer	Sequential etch, micro-section reference	2–4 days	Medium–High
16+ / HDI	Etch + precision milling + X-ray assist	3–7 days	High

Each exposed layer is scanned at the same resolution before proceeding to the next. The process is destructive—once a layer is etched away, it cannot be re-examined, which is why scan quality control at every step is non-negotiable. For HDI boards with stacked microvias and build-up layers, the process requires even finer control; our HDI PCB copy guide covers those specifics.

Stage 5 — CAD Tracing and Reconstruction

Layer scans are imported into professional PCB CAD software (Altium Designer, PADS, or Cadence Allegro). Engineers trace every pad, trace, via, and copper pour manually or semi-automatically. Automated bitmap-to-vector conversion handles large ground planes and regular trace patterns, but complex routing—especially differential pairs, serpentine length-matching, and fine-pitch BGA fan-outs—is verified and corrected by hand.

Trace widths are measured against the calibrated scan. Our standard tolerance target is ±0.5 mil for traces ≥ 6 mil and ±1.0 mil for traces in the 3–5 mil range. Pad diameters and annular rings are matched to the original within ±0.3 mil. For context on how tight these numbers really are, see our breakdown of reverse-engineering accuracy and what affects it.

Via types—through-hole, blind, buried, micro—are classified and their drill sizes recorded. Stackup parameters (dielectric thickness, copper weight) are either measured from a micro-section or inferred from the board’s overall thickness and layer count.

Stage 6 — Netlist Verification and DRC

This is the quality gate. The reconstructed design’s netlist is extracted and compared against the physical board using continuity testing on a sample set of critical nets. We also run a full design-rule check (DRC) against IPC-2221 and the target fabricator’s capabilities:

• Minimum trace/space: verified against fab capability (typically 3/3 mil for standard, 2/2 mil for HDI)
• Annular ring: ≥ 3.5 mil for through-hole vias, ≥ 2.5 mil for microvias
• Drill-to-copper clearance: ≥ 8 mil standard
• Impedance-controlled nets: stackup is calculated to match target impedance (typically 50 Ω single-ended, 90–100 Ω differential) within ±10%

If DRC flags violations, the engineer reviews whether the violation exists on the original board or was introduced during tracing. Original-board violations are documented but preserved; introduced errors are corrected.

Stage 7 — File Output and Delivery

The final deliverable package includes:

• Gerber files (RS-274X) — one per copper layer, solder mask, silkscreen, paste
• Excellon drill file with tool table
• Pick-and-place centroid file (CSV)
• Bill of materials (Excel/CSV)
• Board stackup drawing (PDF)
• Schematic (if ordered) in PDF and native CAD format

Files are packaged in a zip archive and delivered electronically. Turnaround from board receipt to file delivery varies by complexity—our turnaround time breakdown gives specific ranges by layer count and board class.

What Can Go Wrong at Each Stage?

Transparency about failure modes is part of honest engineering. Here are the most common issues and how we handle them:

Stage	Common Problem	Impact	Mitigation
Intake	Hidden internal damage not visible externally	Layer data loss during delayering	X-ray pre-inspection on suspect boards
Component removal	Pad lift on aged or lead-free boards	Lost pad geometry	Lower-temperature desoldering; reference second board if available
Scanning	Residual solder mask obscuring traces	Missed thin traces	Selective mask stripping with NaOH solution
Delayering	Over-etch destroying adjacent layer	Irreversible data loss	Incremental etch with frequent inspection
CAD tracing	Misidentified via type (blind vs. buried)	Fabrication failure	Cross-section verification sample
Verification	Impedance mismatch from wrong dielectric assumption	Signal integrity issues on high-speed nets	Measure dielectric constant from micro-section or request OEM stackup data

For a deeper look at errors that derail projects, read about mistakes that commonly slow PCB copy projects down.

Do You Need the Original Schematic?

No. The pcb copy process works from the physical board alone. A schematic can be reverse-engineered from the extracted netlist and BOM, but it is not a prerequisite for producing Gerber files. If your original design files are lost, recovering the schematic from the board itself is a standard add-on service.

How Layer Count Changes the Process

A 2-layer board can often be fully scanned and traced in 2–3 working days. A 4-layer board adds a day for delayering and inner-layer scanning. Beyond 6 layers, the process scales roughly linearly—each additional layer pair adds 0.5–1 day of delayering and 0.5–1 day of tracing, depending on routing density.

The real complexity jump happens not at a specific layer count but when the board introduces HDI features: stacked microvias, sequential lamination, and via-in-pad. These require more careful delayering and more cross-section references. If you are evaluating whether your board is a candidate, our page on multilayer board copying and what layer count changes gives practical guidance.

Equipment and Tools Used

Professional PCB reverse engineering relies on calibrated, purpose-built equipment. The core toolchain includes:

• Flatbed scanner / area-scan camera: 2400–4800 DPI, color-calibrated, with distortion correction
• Stereo microscope: 7×–45× for component ID and fine-trace inspection
• X-ray system: for BGA pad mapping and internal via verification without destructive delayering
• Chemical etch station: temperature-controlled baths for repeatable layer removal
• Micro-sectioning saw and polisher: for cross-section analysis of stackup and via structures
• LCR meter and curve tracer: for passive component value verification and semiconductor identification
• CAD software: Altium Designer, Cadence Allegro, or Mentor PADS for reconstruction

How long does the entire PCB copy process take?

A simple 2-layer board typically takes 3–5 working days from board receipt to file delivery. A 4-layer board runs 5–8 days. Complex multilayer or HDI boards (8+ layers) range from 10–20 working days depending on routing density, via structures, and whether a schematic is included in the deliverables.

Is the original board destroyed during copying?

For 2-layer boards, the process is non-destructive—your board is returned intact. For multilayer boards, delayering is destructive by nature: copper layers are chemically removed to expose inner layers. If you need the board preserved, we recommend sending two samples—one for delayering and one as a reference.

Can the PCB copy process reproduce impedance-controlled traces?

Yes. Trace geometry is captured during scanning and tracing. Impedance is then calculated using the reconstructed stackup (dielectric thickness, copper weight, trace width/spacing). We target ±10% impedance accuracy on controlled nets. For best results, providing the original stackup specification—or a second board for micro-section analysis—reduces uncertainty.

What if my board has potted or conformal-coated areas?

Conformal coating (acrylic, silicone, urethane) is chemically stripped before scanning. Potting compound over specific sections is mechanically removed. Both add 0.5–1 day to the process. In rare cases, aggressive potting removal can damage underlying traces; we assess this risk during intake and flag it before proceeding.

What file formats are delivered at the end?

Standard deliverables are Gerber RS-274X, Excellon drill files, BOM (Excel/CSV), pick-and-place centroid (CSV), and a stackup drawing (PDF). Native CAD project files (Altium .PcbDoc, PADS .pcb, or Allegro .brd) are available on request. Schematics, when ordered, are delivered in PDF and the native CAD format of your choice.

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