To reverse engineer a PCB, preserve the original board’s evidence, identify components, map connections, reconstruct the design and validate the resulting files against the hardware. The difficult part is deciding what is confirmed and what remains an assumption. A convincing layout drawing can still contain an incorrect pin assignment, a missing internal connection or a guessed component value.
This guide explains how to reverse engineer a PCB with a traceable record from sample to deliverables. It covers authorized recovery for maintenance, documentation and replacement projects. The workflow is a planning framework, not a claim that every board can be recovered completely. For project assessment, see our PCB reverse engineering service scope.
1. Define the evidence and the required outcome
Begin with the decision the recovered design must support. Repair documentation may need a verified power circuit and connector map. A replacement board can also require editable CAD, fabrication data, assembly information, firmware and an equipment-level acceptance plan. Agree which outputs are included before committing a sample to analysis.
Record the sample’s board revision, assembly variant, condition and origin. A repaired board may contain modifications that should not automatically become part of the recovered design. If two samples disagree, investigate the difference instead of silently combining them. Keep the physical observation separate from the interpretation.
| Question | Evidence to retain | Status to record |
|---|---|---|
| Which board is being recovered? | Revision markings, serial label, full-board photographs and sample identifier | Confirmed revision or unresolved variant |
| Does pad A connect to pad B? | Annotated copper image and recorded electrical check with probe locations | Observed, measured or still inferred |
| What is component U3? | Top marking, package dimensions, pin orientation and manufacturer document | Exact identity or candidate part |
| Can the replacement perform its job? | Defined inputs, loads, configuration and comparison results | Passed, failed or not tested |
Give each unresolved item an owner and a next action. “Unknown capacitor value at C17” is useful; “BOM nearly complete” hides the same risk. This register becomes the release checklist and makes partial recovery understandable to the next engineer.
2. Capture a baseline before disassembly
Photograph both faces, board edges, connectors, jumpers and component markings before cleaning or removing parts. Include a dimensional reference and record which face is shown. Keep untouched image files alongside annotated copies. Establish a coordinate origin and consistent orientation so a bottom-side image cannot accidentally be interpreted as a top-side view.
Measure mounting features and connector positions against the intended enclosure. Capture the board outline independently of the copper image: lens distortion and an incorrect scale can produce a neat-looking layout that does not fit. Choose imaging resolution by whether the smallest required feature can be distinguished and measured; a universal DPI target is not a substitute for checking the actual image.
Record any known operating baseline before invasive work, using an approved test setup. Start with the board de-energized for resistance and continuity measurements, with stored energy safely discharged. Work on mains or high-energy equipment requires appropriate isolation and competent personnel. Do not power an unidentified board merely to see whether it starts.
Agree which sample may be altered. Selective component removal can expose obscured pads, but it can also destroy markings, disturb configuration or damage the only working reference. For multilayer or potted assemblies, establish an inspection plan and explicit stop points before destructive access. Imaging feasibility depends on the structure; neither outer photographs nor a generic X-ray promise establishes every hidden connection.
3. How to reverse engineer a PCB into connections and component identities
Build the component register and connectivity map together. Assign reference designators, record package and orientation, then trace accessible paths between identified pads. Use neutral temporary net names while a function remains uncertain. Calling a conductor “ground” because it looks like a large copper area can conceal isolated returns or a different supply domain.
A continuity indication alone does not prove that two points share uninterrupted copper. Parallel components, low-resistance paths and semiconductor junctions can complicate in-circuit measurements. Record the measurement conditions and resolve ambiguity with additional evidence or agreed selective isolation. Preserve the distinction between a copper connection and a path through a component.
For IC identification, begin with the actual logo and marking. The Texas Instruments part-marking lookup accepts package markings or TI part numbers. Treat a search result as a candidate until its package, orientation and pin functions agree with the sample. Similar text on a package does not establish the complete orderable part or electrical grade.
Illustrative pin-check example: the eight-pin package diagram in TI’s LM358-family datasheet, SLOS068AB identifies pin 4 as V− and pin 8 as V+. After confirming the applicable device and package, compare those pins with the observed supply connections. A contradiction is a reason to revisit orientation, identification or tracing. It is not a reason to force the recovered schematic to resemble a familiar application circuit. This is a documentation example, not a measurement from a customer board.
Organize the schematic into readable functional blocks while retaining a cross-reference to physical designators. Record passive measurements with the measurement method and whether the part was isolated. A measured capacitance does not establish voltage rating, dielectric or temperature behavior. Keep unsupported attributes open rather than choosing convenient catalogue defaults.
Firmware, programmable logic, configuration and calibration are separate evidence tracks. Recovering copper and a BOM does not establish access to these contents or reproduce their behavior. Identify the dependencies early, including any authorized source files or programming records the owner can supply.
4. Validate each deliverable against independent evidence
A drawing should be checked against the board, not only against another drawing generated from the same assumptions. Cross-check critical connector paths, power domains and pin numbering using the preserved images and measurement record. Where practical, have a second reviewer trace selected high-consequence nets from the evidence without seeing the first interpretation.
The KiCad 9.0 PCB Editor manual describes design-rule checks against configured board requirements and connectivity. Its schematic-parity option also checks differences between schematic and PCB, but has no effect in standalone PCB Editor mode. Run the appropriate checks and document exclusions. The engineering implication is straightforward: a clean CAD report cannot validate an incorrectly reconstructed source netlist.
| Deliverable | Independent check | What it does not establish |
|---|---|---|
| Schematic and net map | Selected paths and pin assignments compared with sample evidence | Component ratings or firmware behavior |
| Editable PCB layout | Mechanical measurements, layer evidence and schematic parity | Unknown laminate properties or unmeasured impedance |
| BOM and assembly data | Reference, quantity, package, orientation and exact part checks | Automatic suitability of substitute components |
| Fabrication package | Exported layers, outline and drill registration reviewed together | A complete editable engineering project |
| Functional report | Recorded results against agreed operating conditions and limits | Untested modes, lifetime or product certification |
Inspect exported production files separately from the CAD view. Check layer identification, units, drill alignment, outline and required manufacturing notes. Ucamco’s official Gerber format downloads list the layer specification, job format and XNC drill format separately. Agree the fabricator’s accepted package rather than assuming one file extension communicates every requirement.
If starting from existing Gerbers, inspect their metadata as well as geometry. KiCad’s Gerber Viewer documentation describes X2 metadata support and explains the limits of exporting copper into an editable PCB representation. That conversion does not automatically recreate a normal, fully reconstructed design project. Scope missing schematic and component information explicitly.
For a replacement assembly, define staged prototype tests: unpowered checks, controlled initial power, then the specified interfaces and loads. Choose limits from the equipment requirements and established reference behavior, not a universal current percentage. Record failures and untested conditions. A revision must return to the affected evidence and repeat the relevant checks before release. Our PCB copy deliverables guide helps distinguish file recovery from a replacement-board project.
5. Follow an evidence-based workflow
- 1 · Define the recovery boundaryList required outputs, sample permissions and acceptance criteria.
- 2 · Preserve the baselineArchive sample identity, photographs, dimensions and known behavior.
- 3 · Collect and classify evidenceSeparate observed features, measurements, interpretations and unknowns.
- 4 · Reconstruct the designBuild linked component, connection, schematic and layout records.
- 5 · Challenge the reconstructionCheck independent evidence, CAD consistency, exports and agreed functions.
- 6 · Release with a clear statusPackage accepted files, evidence references and any unresolved limitations.
Keep revisions together in a manifest: sample ID, file names, CAD version, source documents, checker and release status. Mark superseded exports clearly. Otherwise a correct schematic can be paired with an earlier drill file or a BOM from another assembly variant.
6. Resolve these questions before proceeding
Can photographs alone produce manufacturing-ready files?
Photos can support identification and visible-route interpretation. They do not verify obscured copper, hidden layers, all component properties or functional behavior. Record a photo-only result as preliminary unless the required evidence has been obtained through other means.
Must every board be stripped or destroyed?
No universal rule applies. The required deliverables, accessible routing and remaining uncertainty determine the inspection plan. Preserve a working reference where possible, and obtain agreement before altering the only sample.
What should I send for a feasibility review?
Send clear photographs of both sides, visible board and chip markings, available design files, sample quantity and condition, intended use, known uncertainties and required outputs. State whether firmware or configuration is available and whether a sample may be altered.
Use our project examples to discuss a comparable scope, then request a review of your actual evidence. A useful proposal identifies the recovery boundary, remaining questions and acceptance method before committing to production.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
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