What Is IC Decapsulation and Why Does It Matter?
IC decapsulation is the controlled removal of a chip’s packaging material—epoxy mold compound, ceramic lid, or metal can—to expose the bare silicon die underneath. It is a prerequisite for die-level failure analysis, firmware recovery via micro-probing, visual inspection of bond wires, and reverse engineering of analog or mixed-signal layouts. Whether the process succeeds without damaging the die depends on five measurable factors that our engineers evaluate before any acid touches the package.
How Does the IC Decapsulation Process Work?
There are three primary decapsulation methods used in professional labs. Each trades speed against control, and the right choice depends on the package construction and the goal of the exposure.
Chemical (Wet) Decapsulation
The most common technique. Fuming nitric acid (HNO₃, 90–98% concentration) or sulfuric acid (H₂SO₄) is applied to dissolve the epoxy mold compound. The acid is heated to 60–80 °C and directed onto the package surface through a jet-etch system or applied in a controlled cavity. Typical etch times range from 45 seconds for thin QFN packages to 8+ minutes for large BGA modules with thick overmold. The process must stop before acid reaches bond pads or aluminum metallization, which dissolves rapidly in hot nitric acid.
Laser Decapsulation
A pulsed Nd:YAG or fiber laser ablates the mold compound layer by layer. This method offers spatial precision down to roughly 25 µm, making it ideal for exposing specific regions of a die without opening the entire package. Laser decapsulation works well on packages where the die is offset or where only a corner needs inspection. The downside: it is slower per unit area and can induce thermal shock if pulse energy is too high.
Mechanical (Plasma/Grinding) Decapsulation
CNC milling or plasma etching removes material mechanically or via reactive ion bombardment. Plasma decapsulation using an O₂/CF₄ gas mixture is the gentlest option—it cannot damage metal layers—but it is extremely slow, sometimes requiring 4–6 hours for a single package. It is reserved for high-value parts where zero risk to the die is mandatory.
| Method | Precision | Speed | Risk to Die | Best For |
|---|---|---|---|---|
| Chemical (acid jet) | ±200 µm | 1–10 min | Moderate | Standard epoxy packages (QFP, SOIC, QFN) |
| Laser ablation | ±25 µm | 5–30 min | Low–moderate | Localized exposure, stacked die |
| Plasma etch | ±50 µm | 2–6 hours | Very low | High-value die, gold bond wires |
| CNC grinding | ±100 µm | 3–15 min | High | Ceramic / metal-can packages |
Five Factors That Determine IC Decapsulation Feasibility
Not every chip can be successfully decapsulated. Our lab evaluates these five variables during a feasibility assessment, typically within 1–2 working days of receiving the part.
1. Package Type and Mold Compound
Standard epoxy-based packages (SOIC, TQFP, QFN, BGA) respond predictably to acid. Ceramic packages (CERDIP, CLCC) require mechanical lid removal—usually straightforward. Metal-can packages (TO-3, TO-8) need careful grinding or prying. The real challenge emerges with newer fan-out wafer-level packages (FOWLP) and embedded-die substrates, where the die is encased in redistribution layers only 50–100 µm thick. Acid over-etch in these structures destroys the die in seconds.
2. Die Size and Location Within the Package
A die that occupies 60–80% of the package footprint is easier to expose without over-etching the edges. Small die in large packages—common in power management ICs—require precise X-ray imaging first to locate the die paddle. We use a Dage or Nordson X-ray system at 80–130 kV to map die position, bond wire routing, and any internal shielding before selecting the etch window. Without this step, blind etching wastes samples.
3. Bond Wire Material
Gold bond wires survive nitric acid well. Copper bond wires dissolve in it. Aluminum wedge bonds are vulnerable to prolonged exposure. If the chip uses copper wires—increasingly common in automotive and consumer parts since ~2010—we switch to sulfuric acid or laser decapsulation, both of which preserve copper. Identifying wire material before starting is non-negotiable; a wrong acid choice severs every connection in under 30 seconds.
4. Number of Available Samples
IC decapsulation is partially destructive. Even with optimal technique, first-attempt success rates in our lab average 85–92% for standard packages and drop to 60–75% for advanced packaging (WLCSP, flip-chip, 3D stacked). We recommend providing a minimum of 3 samples for standard parts and 5+ for advanced packages. If only one sample exists, we use the most conservative method—plasma etch—regardless of time cost.
5. Protection and Passivation Layers
Some ICs include anti-tamper mesh layers, active shields, or thick polyimide passivation specifically designed to resist decapsulation. Chips from secure-element families (e.g., Infineon SLE series, NXP SmartMX) feature metal shields that trigger memory erase upon breach. For standard microcontrollers like the STM32F1 family, passivation is a standard SiN/SiO₂ layer that can be removed with buffered HF after decapsulation. But higher-security parts may be physically impossible to decapsulate without destroying the stored data.
What Can Go Wrong During Decapsulation?
Our engineers have processed thousands of parts. These are the failure modes we see most often, and how we mitigate them:
- Over-etch: Acid dissolves bond pads or metallization. Mitigation: timed etch with optical endpoint detection; we check under a stereo microscope every 30 seconds during the final phase.
- Thermal cracking: Rapid temperature changes crack the die or delaminate it from the paddle. Mitigation: pre-heat the package to 50 °C before acid application; cool gradually.
- Bond wire lift: Mechanical stress or acid undercutting detaches wires from the die. Mitigation: minimize acid volume, use jet-etch to direct flow away from wire bonds.
- Contamination: Residual acid or mold compound particles on the die surface obscure features. Mitigation: sequential rinse in acetone, IPA, and DI water; ultrasonic bath at 40 kHz for 60 seconds.
- ESD damage: Exposed die is extremely sensitive to electrostatic discharge. Mitigation: all post-decap handling on grounded ESD mats with wrist straps; storage in conductive gel packs.
IC Decapsulation for Firmware Recovery and Code Reading
One of the most common reasons clients request IC decapsulation is to access firmware stored in on-chip flash or EEPROM when standard programming interfaces are locked. After exposing the die, micro-probing stations with tungsten needles (tip radius ~1 µm) can tap internal bus lines to extract data. This is a specialized extension of our code reading services, and it applies only to parts where the protection scheme can be bypassed at the silicon level.
Not all chips yield to this approach. Parts with encrypted flash, active mesh shields, or fuse-blown JTAG ports may resist even after successful decapsulation. We always run a feasibility check first and report honestly when a part is beyond recovery.
Which Chip Families Respond Well to Decapsulation?
Success varies dramatically by vendor and process node. Here is a general guide based on our lab experience:
| Chip Category | Decap Difficulty | Typical Method | Notes |
|---|---|---|---|
| 8-bit MCUs (PIC, AVR, 8051) | Low | Chemical | Large die, simple passivation |
| STM32 Cortex-M series | Low–Medium | Chemical or laser | Standard SiN passivation; see STM32F2 unlock feasibility |
| Automotive MCUs (Renesas RH850, NXP S32K) | Medium | Chemical with Cu-safe acid | Copper bond wires common |
| FPGAs (Xilinx, Intel/Altera) | Medium–High | Laser + plasma | Large die, multiple metal layers |
| Secure elements (NXP, Infineon) | Very High | Plasma only | Active shields; data often destroyed |
| Legacy analog ICs (Fairchild, ON Semiconductor) | Low | Chemical | Older process nodes, no anti-tamper |
Our Decapsulation Workflow
- Intake and X-ray: We X-ray every sample to map die position, wire material, and internal structure. Turnaround: same day.
- Method selection: Based on X-ray results, package datasheet, and client goals, we choose the optimal decapsulation method.
- Controlled etch: Decapsulation proceeds with real-time optical monitoring. We photograph intermediate stages.
- Post-decap inspection: Die surface is inspected under 200–1000× optical microscope. Bond wire integrity is verified.
- Deliverable: Exposed die ready for micro-probing, imaging, or further analysis. We provide high-resolution die photographs with the report.
Typical turnaround for the complete process is 3–5 working days. Rush service (1–2 days) is available for standard packages with adequate sample quantity.
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Request a feasibility reviewFrequently Asked Questions
Is IC decapsulation destructive to the chip?
IC decapsulation removes the package permanently, so the chip cannot be resoldered onto a board afterward. However, the die itself and its stored data can remain fully intact if the process is performed correctly. For firmware recovery, the die only needs to be electrically functional at the pad level—it does not need its package.
How many sample chips should I send for decapsulation?
We recommend a minimum of 3 identical samples for standard packages (QFP, SOIC, QFN) and at least 5 for advanced packages like WLCSP or flip-chip BGA. If you have only one chip, we will use the slowest, safest method (plasma etch), but success is not guaranteed and turnaround extends to 5–7 working days.
Can you decapsulate a BGA without damaging the die?
Yes, in most cases. BGA packages with standard epoxy overmold respond well to chemical jet-etch from the top side. Flip-chip BGAs—where the die faces downward—require backside access through the substrate, which is more complex but achievable with laser or plasma methods. We X-ray every BGA first to determine die orientation.
What is the difference between decapsulation and delidding?
Delidding refers specifically to removing a metal or ceramic lid from a hermetically sealed package (e.g., CERDIP, metal-can TO-style). Decapsulation is the broader term covering any package-removal technique, including acid etching of epoxy mold compounds. Delidding is generally simpler and lower-risk than chemical decapsulation.
Do I need to prove ownership before you decapsulate my chip?
Yes. IC decapsulation for firmware recovery or design analysis requires proof that you own the IP or the hardware containing it. We operate under NDA and verify authorization before beginning work. See our STM32L4 unlock page for a typical authorization workflow example.
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