Impedance controlled PCB reverse engineering means recovering not just the copper pattern but the electrical stackup behind it — layer order, dielectric thicknesses, copper weights, laminate Dk, and the exact trace width and spacing that made a pair land on 90 Ω or 100 Ω. Copy the artwork alone and the board will look identical, fabricate fine, and fail eye-diagram or return-loss testing. That’s the whole job: geometry plus material, verified against measurement.
If your board carries USB, Ethernet, LVDS, DDR, MIPI, PCIe, SDI, or an RF front end, this is the version of reverse engineering you need.
Why an ordinary board copy breaks a controlled impedance design
A standard copy captures nets and footprints. That’s fine for a relay board. On a high-speed board the electrical behavior lives in dimensions the artwork doesn’t record.
Three things go wrong most often. First, the fabricator substitutes a stackup — same layer count, different prepreg thicknesses — and a 5 mil trace that was 50 Ω becomes 58 Ω. Second, the copy shop redraws a differential pair without preserving intra-pair spacing, so the coupling changes and the pair drifts off target. Third, nobody records the laminate. A standard FR-4 at Dk 4.3 and a mid-loss laminate at Dk 3.7 give very different results with identical copper.
You usually don’t see the failure at power-up. You see it as marginal link training, occasional CRC errors, or an EMC test that passes on the original and fails on the copy. That’s why the accuracy question in reverse engineering matters more here than on almost any other board type — accuracy has to include the Z axis, not just X and Y.
What we actually measure on your board
Cross-section and stackup
We take a sample coupon from a non-critical edge of a spare board, pot it, polish it, and cross-section it under a metallurgical microscope. From that section we read core and prepreg thicknesses, plated copper thickness on the outers, base copper on the inners, and total finished thickness. Where the board has blind or buried vias, the section shows the sub-lamination boundaries.
Copper thickness matters more than people expect. Plating on outer layers is rarely uniform, and etch-back changes the finished trace width relative to the artwork — a trace drawn at 5.0 mil often measures 4.6 mil at the top with a trapezoidal profile. We record the trapezoid, not just a nominal number.
Trace geometry on the layers that matter
Outer-layer geometry we measure optically after cleaning off the solder mask on a sacrificial board. Inner layers come from controlled delamination and layer-by-layer imaging: each layer is scanned, aligned to the drill pattern, and vectorized. Reference planes are noted for every high-speed layer, because a trace referencing a split plane behaves nothing like one over solid ground.
Laminate identification
Sometimes the material is printed on the board or the panel edge. When it isn’t, we work back from the evidence: measured dielectric thickness, glass style visible in section, and the impedance the original design clearly targeted. If a 4 mil dielectric with a 5.5 mil trace only reaches 50 Ω at a Dk near 3.6, the original wasn’t standard FR-4, and we say so in the report rather than guessing silently.
Test coupons and TDR
Most controlled impedance boards carry impedance coupons on the panel edge or in an unused corner. If yours survived, that’s the single most useful artifact you can send us — we TDR it and get the fabricator’s own target values directly. Without a coupon, we build coupons into the first rebuild panel and TDR those instead.
How the process runs, start to finish
- Intake and feasibility. We inspect the samples, confirm layer count by section or X-ray, and identify which nets are impedance-critical. You get a written feasibility note and a quote before anything is destroyed.
- Non-destructive capture. High-resolution scans of both sides, X-ray for internal via structure and BGA pad geometry, component identification and marking capture.
- Destructive analysis on one sample. Cross-section, delamination, inner-layer imaging. This sample does not come back.
- Stackup modeling. We enter the measured geometry into a field solver and check that the calculated single-ended and differential impedances match the coupon TDR data or the obvious design intent. Discrepancies get resolved before layout, not after.
- Data reconstruction. Gerber or ODB++ output, drill files, netlist, BOM, and a stackup drawing with impedance targets and tolerances written on it — the document your fabricator needs.
- Verification build. Optional but recommended: a small prototype run with coupons, TDR report, and side-by-side functional comparison against your original.
The general sequence follows our normal step-by-step reverse engineering workflow, with the cross-section and field-solver stages added on top.
What to send us, and what you get back
Give us this and we can quote quickly:
- Clear photos of both sides on a dark, non-reflective background, whole board in frame, plus close-ups of any fine-pitch or BGA areas.
- Board dimensions and total finished thickness, measured with calipers if you have them.
- Layer count if you know it, and any impedance callouts printed in the silkscreen or on the panel edge.
- Markings on the main chips — the controller, PHY, transceiver, or clock generator tells us what interfaces are on the board and therefore which impedance targets matter.
- Whether you still have an impedance coupon or any fabrication drawing fragment.
- One line on deliverables: Gerbers only, Gerbers plus stackup and impedance report, or full turnkey through verified prototypes.
- Sample count. Two boards is the practical minimum; three is comfortable. One board means we choose between destructive analysis and keeping your reference intact.
Back from us: feasibility assessment, lead time, price, and a clear statement of which impedance values we can verify by measurement versus which we can only model.
Deliverable tiers and what each one is good for
| Tier | Includes | Use it when |
|---|---|---|
| Artwork only | Gerbers, drill files, netlist, BOM | Board has no true high-speed content and you just need to rebuild it |
| Artwork + stackup | Above plus cross-section report, measured dielectrics, copper weights, stackup drawing with impedance targets | You have your own fabricator and want them to hit the original electrical spec |
| Verified impedance package | Above plus field-solver model, coupon design, TDR data from a prototype panel | Ethernet, USB 3.x, DDR, PCIe, LVDS, or anything that has to pass compliance testing |
| Turnkey | Above plus assembly, component sourcing, and functional comparison against your original board | Legacy or obsolete equipment where you need working boards, not files |
Price is driven by layer count, board size, how many nets are impedance-critical, BGA presence and pitch, whether blind or buried vias are involved, and whether you want a verification build. Rigid-flex and mixed-dielectric constructions cost more because there are more sections to cut and more models to run. We quote per board rather than from a rate card.
Where this gets hard, and where it sometimes isn’t feasible
Honest constraints, because they change what you should expect:
Single-sample projects. Cross-sectioning consumes material. With one board we can still model from X-ray and total thickness, but the dielectric numbers become estimates, and we’ll label them as such.
Unknown exotic laminates. On RF boards using PTFE or hydrocarbon-ceramic materials, we can measure thickness precisely but Dk identification is inference unless the material is marked. For narrowband RF that inference is usually good enough after one tuning iteration; for a filter with a tight passband, expect a design spin.
Heavily damaged or burned boards. Delamination that already happened in service destroys the geometry we need. A board with a blown section can often still be reconstructed if the damage misses the critical routing, but the cross-section has to come from clean material.
HDI with stacked microvias and very thin cores. Feasible, but slower and more expensive. Each sub-lamination needs its own section and its own model.
Buried resistors, embedded capacitance layers, and buried passives. These show up in section but their values are not directly readable. We flag them and work with you on a functional equivalent.
Length matching and via structures. Recovering matched lengths and stub geometry is achievable, but if the original relied on back-drilling, that has to be specified explicitly in the rebuild drawing or the fabricator will skip it.
We work on boards whose design rights belong to the customer — recovering your own lost design data, supporting equipment you own, handling obsolescence, or performing failure analysis. You confirm you hold the rights; we run everything under NDA. If you want the longer answer, see our note on the legality of reverse engineering.
Typical projects that land here
Most impedance controlled work we see falls into a few buckets. A telecom line card whose original CAD data left with a contractor. A medical imaging front end where the laminate went end-of-life and the design has to be re-qualified on a current material. Motor drives and machine controllers with a gigabit backplane link, which overlaps heavily with our
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.Working on a board like this?
Related reading