What Makes Impedance Controlled PCB Copy Genuinely Difficult?
An impedance controlled PCB copy reproduces not just the copper artwork but the exact electrical environment—dielectric thickness, trace width, copper weight, and laminate Dk—that keeps characteristic impedance within a ±5–10% window of the original design intent. Most copy houses capture geometry and stop there. Signal integrity fails on the clone because nobody reconstructed the stackup math that makes a 50 Ω microstrip actually measure 50 Ω.
The challenge compounds on boards running differential pairs at 100 Ω, LVDS at 85 Ω, or USB 3.x at 90 Ω ±5%. A 0.5 mil error in dielectric height or a 0.2 shift in Dk can push impedance outside spec, producing eye-diagram failures that don’t show up until the board is populated and powered.
Why Standard PCB Copying Fails on Impedance-Critical Boards
A typical PCB copy workflow—scan layers, vectorize traces, generate Gerbers—captures XY geometry. That’s roughly 60% of the information needed for an impedance controlled design. The missing 40% lives in the Z-axis:
- Prepreg and core thickness — measured per layer pair, not assumed from a generic catalog.
- Dielectric constant (Dk) — varies from 3.2 (Megtron 6) to 4.7 (standard FR-4) and shifts with frequency. The wrong Dk invalidates every impedance calculation.
- Copper roughness profile — RTF, VLP, or HVLP foil changes effective Dk at frequencies above 3 GHz by up to 8%.
- Solder-mask thickness over traces — adds 2–5 Ω to microstrip impedance if unaccounted for.
Without recovering these parameters, a geometrically perfect Gerber set will still produce a board that fails TDR verification.
How We Reconstruct Impedance Stackups — Step by Step
1. Cross-Section Microsectioning
We cut the original board at multiple controlled-impedance trace locations and photograph the cross-section at 200–500× magnification. This gives us actual copper width (top and bottom of the trapezoidal etch profile), dielectric height to the nearest 0.1 mil, and copper thickness per layer. On a 10-layer board, we typically take 4–6 cross-sections.
2. Laminate Identification
We identify the laminate system through a combination of color, texture, burn test, and—when necessary—FTIR spectroscopy. Common identifications include Isola 370HR (Dk 3.92 @ 1 GHz), Panasonic Megtron 4 (Dk 3.4), and Rogers 4350B (Dk 3.48). Getting this wrong by even one material grade can shift impedance 6–12%.
3. Field-Solver Modeling
We feed measured geometry and identified Dk into a 2D field solver (Polar Si9000 or equivalent) to calculate characteristic impedance for every controlled-impedance net class. If the calculated value matches the original design’s target (typically printed on the fab drawing or implied by the interface standard), we lock the stackup. If not, we iterate dielectric assignments until the model converges within ±2 Ω.
4. Stackup Documentation and Fab Notes
The final deliverable includes a fully specified stackup table—layer order, copper weights, prepreg/core part numbers, dielectric thicknesses, impedance targets, and test coupon requirements. This is what separates a reproducible impedance controlled PCB copy from a one-off guess.
Critical Tolerances We Track
| Parameter | Typical Target | Our Measurement Resolution | Failure Impact if Missed |
|---|---|---|---|
| Trace width (microstrip) | 4–8 mil | ±0.1 mil | ±3–5 Ω per 0.5 mil error |
| Dielectric height | 3–10 mil | ±0.1 mil | ±2–4 Ω per 0.5 mil error |
| Dk (laminate) | 3.2–4.5 | Material ID + datasheet | ±6–12 Ω if wrong material assumed |
| Copper thickness | 0.5–2.0 oz | ±0.05 mil | Etch profile and skin-effect shift |
| Differential pair spacing | 4–12 mil | ±0.1 mil | ±3–8 Ω on 100 Ω diff pairs |
| Solder mask over trace | 0.3–1.0 mil | ±0.1 mil | +2–5 Ω on outer-layer microstrip |
Where Impedance Control Intersects Other Board Complexities
Impedance controlled routing rarely exists in isolation. The boards that need it tend to also carry:
- High-density BGA breakout — differential pairs routed through 0.8 mm pitch BGA fields demand length-matched, impedance-continuous escape routing. We handle these in our BGA PCB copy and escape-routing reconstruction workflow.
- High-frequency laminates — boards mixing FR-4 cores with Rogers or Megtron signal layers require hybrid stackup documentation. Our high-frequency PCB copy process covers mixed-dielectric identification.
- Rigid-flex transitions — impedance changes at the rigid-to-flex boundary because polyimide Dk (≈3.2–3.4) differs from FR-4. See our approach to rigid-flex PCB cloning with impedance continuity across transition zones.
- RF microstrip and stripline — 50 Ω RF transmission lines on dedicated signal layers are common in RF board reverse engineering, where even via stub length matters.
Common Failure Modes We’ve Seen on Other Shops’ Copies
We regularly receive “failed clone” boards from engineers who tried another vendor first. The patterns repeat:
- Generic FR-4 assumed everywhere. The original used Isola I-Tera MT40 (Dk 3.45). The copy used standard FR-4 (Dk 4.2). Every 50 Ω trace measured 58 Ω. USB 3.0 link training failed.
- Stackup height guessed, not measured. A 6-layer board had 5.2 mil prepreg between layers 1–2. The copy shop used their default 4.5 mil. Impedance dropped 7 Ω across all outer-layer traces.
- Differential pairs re-routed for “cleanup.” The copy shop straightened differential pairs to look neater, breaking length matching and changing coupling. Skew exceeded 5 ps, failing HDMI compliance.
- No TDR verification on the clone. Without measuring the finished board, nobody caught that the fab shop substituted a different prepreg resin system.
What You Receive in an Impedance Controlled PCB Copy Deliverable
| Deliverable | Format | Details |
|---|---|---|
| Gerber file set | RS-274X / Gerber X2 | All copper, mask, silk, drill layers |
| Stackup specification | PDF + ODB++ stackup | Layer order, materials, thicknesses, Dk values, impedance targets |
| Impedance table | Excel / PDF | Net class, target Zo, trace width, dielectric height, calculated Zo |
| BOM (if requested) | Excel | Component identification with manufacturer part numbers |
| Fab notes | IPC class, test coupon requirements, TDR acceptance criteria | |
| Schematic (if requested) | PDF + source (Altium/KiCad) | Full netlist-verified schematic |
Industries Where Impedance Controlled Copies Are Most Requested
Telecom infrastructure boards (10G/25G SerDes), medical imaging systems, automotive radar modules (77 GHz — where even via transitions need impedance modeling), and precision instrumentation with high-speed ADC front ends. In each case, the board won’t function at spec without impedance fidelity in the clone.
Turnaround and Pricing Factors
An impedance controlled PCB copy typically takes 8–15 working days depending on layer count and laminate complexity. Pricing runs 30–60% higher than a standard copy of equivalent layer count because of microsectioning, material identification, and field-solver modeling. A 6-layer board with two impedance classes and standard FR-4 sits at the lower end. A 14-layer hybrid-laminate board with five impedance classes and blind/buried vias sits at the upper end.
We provide a detailed quote within 48 hours of receiving the board or high-resolution photos of both sides plus a layer-count estimate.
[pcb_cta type=”quote”]
Frequently Asked Questions
Can you copy an impedance controlled PCB without destroying the original board?
Microsectioning requires cutting a small sample—typically from a scrap area or a second sacrificial unit. If only one board exists, we can use non-destructive methods (precision calipers on delaminated layers, known-material databases, and TDR measurements on the assembled board) to approximate the stackup, though accuracy drops from ±2 Ω to roughly ±5 Ω.
What if the original laminate is discontinued?
We identify a substitute with matching Dk, Df, Tg, and CTE from current production catalogs. For example, Nelco N4000-13 EP SI is commonly replaced by Isola I-Speed. We recalculate trace widths in the field solver so impedance targets are met on the replacement material.
Do you verify impedance on the fabricated clone?
Yes. We specify TDR test coupons on the fab panel and require the fabricator to provide a TDR report per IPC-2141A. We review the report before shipping Gerbers as “production verified.” If the first run fails TDR, we iterate the stackup at no additional engineering cost.
How does solder mask affect impedance on outer layers?
Solder mask (Dk ≈ 3.3–3.8) over a microstrip trace lowers the effective impedance by 2–5 Ω depending on thickness. We model this explicitly in the field solver. Some designs use solder-mask-defined impedance intentionally; others require mask relief over critical traces. We replicate whichever approach the original used.
Can you handle differential impedance as well as single-ended?
Absolutely. We reconstruct both single-ended (e.g., 50 Ω microstrip, 50 Ω stripline) and differential (e.g., 90 Ω USB, 100 Ω LVDS, 85 Ω HDMI) impedance classes. Each class gets its own entry in the impedance table with trace width, spacing, and dielectric height specified independently.
Related Board-Type Capabilities
- Heavy-copper PCB copy for power-and-signal hybrid boards
- Automotive ECU PCB copy with impedance-critical CAN/FlexRay routing
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote