Military PCB reverse engineering is priced by layer count, board area, component count, and whether firmware recovery is part of the job — not by a flat rate. A conformally coated four-layer control board with a few hundred parts is typically a one-to-two week job for full schematic and Gerber recovery. A twelve-layer backplane with BGAs, buried vias, and an obsolete ASIC runs several weeks. Nobody can quote it from a description alone; it needs photos and the board.
The rest of this page explains what actually drives those numbers, so you can estimate before you ask, and defend the estimate to whoever signs the purchase order.
What makes a military board different from a commercial one
The electrical design is often simpler than a modern consumer board. The difficulty is everything wrapped around it.
Conformal coating and potting. Acrylic coating comes off reasonably well with solvent and controlled abrasion. Silicone is slower. Polyurethane and epoxy potting are the hard cases — you can lose silkscreen, tear pads, and pull small passives off before you get a clean surface to image. Budget real time for coating removal on any avionics, missile, or ruggedized ground vehicle board.
Wide-temp and hi-rel parts with house markings. Defense primes routinely mark parts with an internal drawing number instead of the manufacturer’s part number. A 1N4148 equivalent might read as a JANTX-screened part with a slash sheet number, which is useful, but a custom hybrid marked only with a five-digit CAGE-linked code may take significant lookup work or electrical characterization to identify.
Age. A lot of this work involves boards designed in the 1980s and 1990s. Through-hole is your friend here — netlist tracing is easier. Working against you: oxidized copper, delaminated laminate at the board edges, dried-out tantalum caps that read wrong under test, and gold-plated fingers that have been reworked five times.
Thick copper and heavy ground planes. Power distribution boards in vehicle and shipboard systems often use 3 oz or heavier copper with large pours. That changes how the layers image and it changes the trace-width work if you’re regenerating a manufacturable stack-up rather than just documenting one.
Why the mechanical documentation matters more than usual
Commercial reverse engineering usually stops at Gerbers, BOM, and schematic. Military assemblies often live inside a machined chassis with card guides, tight keep-outs, and a specific connector position tolerance. Board outline, mounting hole positions, and connector datum have to be measured to a tighter standard than a typical PCB copy job, because the replacement has to drop into hardware that nobody is going to remachine. That measurement work adds days, and it is the single most common thing customers forget to ask for.
What actually drives the cost
Here is the honest hierarchy, roughly in order of impact:
- Layer count. Two-layer and four-layer boards are traced from imaged copper on both sides plus inner-layer separation. Every additional inner layer pair adds a separation, imaging, and alignment cycle. Cost does not scale linearly — the jump from six layers to twelve is bigger than the jump from two to six.
- Component count and unique part count. Three hundred resistors of four values are cheap. Sixty ICs of sixty different types are not, because each one needs identification, pinout confirmation, and a symbol.
- Deliverable set. Gerbers and a drill file only? Much faster than Gerbers plus a hierarchical schematic plus a verified netlist plus a BOM with qualified alternates.
- BGA and fine-pitch packages. Ball-out under an FPGA or a large processor has to be resolved through X-ray or by removing the device and imaging the pads. Both add time.
- Coating and potting removal. Can be a half day. Can be a week if the compound fights back.
- Firmware. If the design depends on programmable logic or an MCU whose source is gone, that is a separate workstream with its own feasibility question.
- Sample quantity. Two boards are meaningfully better than one. One board you cannot destructively section is the most expensive case of all.
For reference points on how these factors play out across layer counts, our page on reverse engineering costs and lead times by board type walks through the same variables with more examples.
Realistic lead times, by board class
These are working ranges, not guarantees. A single surprise — a potted module, an unidentifiable custom hybrid — moves any row down a tier.
| Board type | Typical deliverable | Working range | Main risk to schedule |
|---|---|---|---|
| 2-layer through-hole, uncoated, <150 parts | Gerber + schematic + BOM | Several days | Illegible date-coded parts |
| 4-layer mixed SMT/TH, acrylic coated, 200–400 parts | Full package + netlist | 1–2 weeks | Coating removal, house-marked parts |
| 6–8 layer with impedance-controlled runs | Full package + stack-up | 2–3 weeks | Dielectric measurement, layer alignment |
| 10–16 layer with BGA and buried vias | Full package + X-ray records | Several weeks | BGA ball-out, blind/buried via mapping |
| Potted or epoxy-encapsulated assembly | Case by case | Assess first | Damage during decapsulation |
| Any of the above plus firmware recovery | Add a parallel workstream | Add 1–3 weeks | Chip security state, part availability |
Two things compress the schedule more than paying a rush fee. Send more than one sample. And tell us up front which deliverables you actually need — half the time a customer asks for a full schematic when what they need to build boards is a verified Gerber set and a BOM.
What to send us, and what comes back
You do not need to prepare a package. You need to send five things, and it takes ten minutes.
- Photos of both sides. Whole board in frame, dark non-reflective background, even lighting, no flash glare. One extra close-up of any large IC.
- Board dimensions. Length, width, and thickness with a caliper if you have one, a ruler in the photo if you don’t.
- Chip markings. Type out the full marking on the main processor, any programmable logic, and anything with a house part number. Every line of text, including the ones that look like date codes.
- One line on deliverables. “Gerbers only,” “Gerbers plus schematic,” “full package plus five assembled prototypes,” or “we need firmware too.”
- Layer count if you know it. If you don’t, say so — we’ll estimate from edge inspection and confirm on receipt.
What comes back is a feasibility read, a lead time, and a price. If something looks marginal, we say so at that point rather than after taking the money. If the board looks straightforward, the quote is usually turned around the same working day.
The paperwork side
Every project runs under NDA before samples ship. You’re responsible for holding the rights to the design you’re asking us to document, and for compliance with applicable export control and IP law in your jurisdiction — that includes anything ITAR-controlled, which you should assess before shipping hardware across a border. We’re a Shenzhen lab; that constraint is real and it’s yours to manage, and some programs will simply not be able to use an offshore vendor.
Where military PCB reverse engineering gets genuinely hard
Six situations honestly change the answer:
Custom hybrids and screened multi-chip modules. Common in older avionics. If the function is undocumented and the package is hermetic, identification may require decapsulation, and rebuilding an equivalent is a design task, not a documentation task.
Programmable logic with no source. An older CPLD or one-time-programmable PAL in the middle of a control path is a hard dependency. Whether its configuration can be recovered depends entirely on the specific device and its security state. We assess it per part and tell you before you commit.
Single-sample, non-destructive-only. If you have exactly one board, it still has to work, and it’s six layers or more, some of the inner-layer information is only reachable non-destructively through X-ray. That gets you a long way but not always all the way.
Radiation-hardened parts with no drop-in equivalent. Documentation is achievable. Sourcing is a different problem, and we won’t pretend a commercial-grade substitute is equivalent when it isn’t.
Boards that have already been reworked heavily. Cut traces, jumper wires, and added flying leads have to be identified as field modifications rather than original design intent — which means someone has to make a judgment call, and we’ll flag every one of them rather than quietly documenting a repair as a feature.
Severe delamination or corrosion. Recovered from a marine environment, sometimes there’s simply no copper left to trace on part of the board. In that case we document what’s readable and tell you where the gaps are.
Frequently asked questions
Can you reverse engineer a military board if we only have one working unit?
Usually yes, but it constrains the method. With one irreplaceable sample we stay non-destructive: high-resolution imaging both sides, X-ray for hidden layers and BGA ball-out, in-circuit continuity where accessible. On boards up to about six layers that generally produces a complete result. Above that, destructive layer separation gives noticeably better inner-layer confidence, so a second sample — even a known-bad one — is worth finding.
How accurate is the recovered schematic?
Nets are verified by continuity against the physical board, not just read off an image. Passive values are measured, and where a component’s in-circuit reading is ambiguous we mark it as such instead of guessing. We won’t claim perfect accuracy on any board — what we do is tell you exactly which items are confirmed
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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