What Is Multilayer PCB Copy and Why Is It Difficult?
Multilayer PCB copy is the process of reverse-engineering a printed circuit board with four or more copper layers to produce a complete, manufacturable data package—Gerber files, drill files, a BOM, and a validated stackup drawing. The difficulty scales non-linearly with layer count because every added layer introduces hidden copper, buried or blind vias, and dielectric thicknesses that cannot be measured from the surface. On a 12-layer board, for example, roughly 60–70 % of the copper is invisible until the board is physically delayered.
Why Layer Count Changes Everything
A two-layer board can be optically scanned from both sides and traced in hours. A four-layer board adds a ground plane and a power plane that need cross-section analysis. Beyond six layers, the engineering shifts dramatically: signal integrity becomes stackup-dependent, impedance targets are baked into trace geometry and dielectric choice, and via structures branch into blind, buried, and micro-via categories that each require different identification methods.
| Layer Count | Typical Via Types | Stackup Recovery Method | Relative Difficulty |
|---|---|---|---|
| 4 | Through-hole | Cross-section + caliper | Low |
| 6–8 | Through-hole, blind | Cross-section + X-ray | Moderate |
| 10–16 | Through-hole, blind, buried | Micro-section + CT scan + impedance TDR | High |
| 18–32+ | All types + stacked microvias | Sequential delayering + CT + TDR + material lab | Very High |
Our engineers have handled boards up to 32 layers. Beyond 20 layers, turnaround for the full Gerber set typically runs 15–25 working days because each layer must be chemically or mechanically stripped, photographed at high resolution, aligned to fiducials, and traced before the next layer can be exposed.
The Five Hardest Parts of Multilayer PCB Copy
1. Stackup Reconstruction
The stackup defines every dielectric thickness, copper weight, and prepreg/core combination in the board. Get it wrong and impedance, crosstalk, and thermal behavior all shift. We recover the stackup by micro-sectioning at two or three locations, measuring each layer with a calibrated optical microscope (resolution ±0.1 mil), and cross-referencing against known laminate datasheets—typically FR-4, but sometimes Rogers laminates in mixed-dielectric stackups or polyimide flex substrates requiring specific lamination profiles.
2. Buried and Blind Via Mapping
A through-hole via is visible on both surfaces. A blind via connects an outer layer to one or more inner layers. A buried via sits entirely inside the board. X-ray imaging reveals the start and end layers of each via, but on dense 0.3 mm-pitch BGA breakouts, hundreds of vias can overlap in the X-ray projection. We supplement X-ray with sequential delayering and, on critical boards, industrial CT scanning at 5 µm voxel resolution to build a 3D via map before tracing begins.
3. Impedance and Signal-Integrity Recovery
Controlled-impedance traces—50 Ω single-ended, 90 Ω or 100 Ω differential—are defined by trace width, spacing, copper weight, and dielectric constant. Copying the trace geometry alone is not enough; we must reconstruct the impedance environment. After recovering the stackup, our team runs a 2D field solver (matching IPC-2141 methods) to verify that the original trace widths hit the target impedance within ±5 %. If the fabrication house uses a different prepreg batch, we adjust trace widths in the output Gerber to compensate. This step is especially critical on boards requiring high-frequency laminate cloning or RF board reverse engineering with impedance-controlled breakouts.
4. Power-Plane Splits and Thermal Features
Inner-layer power planes often contain splits, relief pads, and embedded thermal vias that are invisible from the outside. Missing a plane split can short two voltage rails or break an isolation boundary. We photograph every inner layer at 1200 DPI minimum and run automated copper-area extraction before manual verification. Boards with heavy copper inner layers (2 oz or above) or embedded coin technology follow our heavy-copper PCB copy workflow to preserve current-carrying capacity.
5. Material Identification
Not every multilayer board is standard FR-4. High-Tg FR-4 (Tg ≥ 170 °C), halogen-free laminates, ceramic-filled PTFE, and polyimide all look similar in cross-section but behave very differently electrically and thermally. We use FTIR spectroscopy and Dk/Df measurement at 1 GHz to identify the base material, then specify an equivalent or identical laminate in the fabrication notes. Misidentifying the material on a 10-layer board can shift differential impedance by 8–12 Ω—enough to cause bit errors on a 5 Gbps SerDes link.
Our Layer-by-Layer Process
- Intake and X-ray survey. Board is photographed, measured, and X-rayed to estimate layer count and via types. Turnaround estimate issued within 1 working day.
- Component removal and BOM capture. Every part is cataloged with manufacturer PN, package, and value. Obsolete parts are flagged with suggested crosses.
- Micro-sectioning. Two to three cross-sections taken at strategic locations to recover the full stackup.
- Sequential delayering. Outer solder mask stripped, then each copper layer chemically etched and scanned at high resolution. Fiducial alignment maintained across all layers.
- Trace extraction and netlist generation. Scanned images vectorized, vias correlated across layers, netlist extracted and compared to the physical board for continuity.
- Impedance verification. Field-solver runs on all controlled-impedance nets. Adjustments noted for target fab house.
- Output package. Gerber RS-274X, Excellon drill, IPC-D-356 netlist, stackup drawing, BOM with alternates, and assembly drawings (top/bottom).
What Can Go Wrong — Honest Caveats
Multilayer PCB copy is not a guaranteed pixel-perfect clone. Here are real failure modes we manage:
- Delamination during delayering. Older boards with moisture absorption can delaminate, destroying one or more inner layers. We mitigate by baking boards at 125 °C for 4–6 hours before processing and keeping a second sample when available.
- Unresolvable BGA fanout. On 0.4 mm-pitch BGAs over 600+ pins, via-in-pad with back-drilled stubs may be present. If the back-drill depth isn’t recoverable, we specify it as a range and flag it in the fab notes.
- Embedded passives. Some multilayer boards embed resistors or capacitors in inner layers. These require destructive analysis and cannot always be replicated by every fab house.
- Proprietary stackups. A few OEMs use custom prepreg thicknesses not commercially available. We specify the closest standard alternative and document the impedance delta.
Multilayer Copy vs. Specialty Substrates
Layer count is one axis of complexity; substrate material is another. Many of the hardest boards we copy are multilayer and built on non-standard materials. A 6-layer board on ceramic substrates for high-reliability applications demands different delayering chemistry than a 6-layer FR-4. A 10-layer mixed-dielectric stackup combining FR-4 cores with PTFE signal layers follows our hybrid stackup PCB copy process. We evaluate each board individually—there is no one-size-fits-all recipe.
Typical Turnaround and Pricing Factors
| Factor | Impact on Time | Impact on Cost |
|---|---|---|
| Layer count (4 vs. 16 vs. 28) | +3–5 days per 4-layer increment | Primary cost driver |
| Blind/buried vias present | +2–4 days for CT scan + mapping | Moderate increase |
| Controlled impedance nets | +1–2 days for TDR + solver | Moderate increase |
| Non-FR-4 material | +1–3 days for material ID | Depends on substrate |
| BGA pitch ≤ 0.5 mm | +1–2 days for fine-pitch fanout | Slight increase |
| Number of unique boards provided | Reduces risk of delayering loss | No extra charge for spares |
For a standard 8-layer FR-4 board with through-hole vias only, expect 8–12 working days. A 16-layer HDI board with stacked microvias and mixed materials can take 20–30 working days. We provide a binding timeline estimate after the X-ray survey.
Deliverable Checklist
- Gerber RS-274X (one file per layer + solder mask + silkscreen + paste)
- Excellon drill files (plated / non-plated separated; blind/buried drill sets)
- Stackup drawing with dielectric thicknesses, copper weights, and material callouts
- IPC-D-356 netlist for bare-board electrical test
- Bill of Materials with MPN, package, value, and alternates
- Assembly drawings (top and bottom) with reference designators
- Impedance report (if controlled-impedance nets present)
How many layers can you reverse-engineer in a single board?
We have successfully completed multilayer PCB copy on boards up to 32 layers. Beyond 24 layers, we require at least two identical sample boards to mitigate the risk of delayering damage destroying critical inner-layer data.
Do you need to destroy the board to copy it?
For boards with four or more layers, yes—delayering is destructive. We strip copper layers sequentially, which means the original board is consumed. If you need the board back intact, we can attempt a non-destructive X-ray-only approach, but accuracy on inner layers drops significantly. Providing a spare board is strongly recommended.
Can you match the original impedance if the exact laminate is discontinued?
Yes. After identifying the original material’s Dk and Df, we select the closest commercially available laminate and adjust trace widths in the Gerber output so that the impedance target (typically 50 Ω ±5 % single-ended or 100 Ω ±5 % differential) is maintained. The impedance report documents both the original and adjusted values.
What file formats do you deliver?
Standard delivery includes Gerber RS-274X, Excellon drill, IPC-D-356 netlist, and a detailed stackup drawing. We can also export ODB++ or Gerber X2 on request at no additional charge.
Is multilayer PCB copy legal?
Reverse-engineering a PCB you own—for legacy maintenance, second-sourcing, or redesign—is legal in most jurisdictions. We require proof of board ownership or authorized access before starting work, and every project is covered by NDA.
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