Multilayer PCB reverse engineering is priced by layer count, board area, component count, and whether the inner layers have to be imaged destructively. A four- or six-layer board of moderate density is typically a matter of days once the sample lands; a dense twelve-layer board with fine-pitch BGAs and blind vias runs into weeks. Nobody can quote it accurately from a description — the price moves with what the board actually looks like under a microscope.
This page explains what drives both numbers, so you can budget before you ask for a quote and recognize a quote that’s been guessed rather than estimated.
What you’re actually paying for
The cost of multilayer work is dominated by one thing: inner layers can’t be photographed from the outside. On a two-layer board an engineer scans top and bottom, traces the copper, and cross-checks continuity with a meter. On a six-layer board, layers 2 through 5 are buried in laminate, and the only way to see them is to remove the material above them.
That means the board goes through controlled delamination or sequential grinding — layer by layer, with high-resolution imaging between each pass. It’s a one-way trip for that sample. Every layer removed is an imaging session, an alignment session, and a tracing session. Six layers isn’t three times the work of two layers; it’s closer to four or five times, because registration error accumulates and has to be corrected against via positions.
The cost drivers, ranked
- Layer count. The single biggest factor. Each internal signal layer adds imaging, alignment, and net tracing hours.
- Board area and copper density. A 300 mm × 200 mm backplane at 4 layers can cost more than a 50 mm square 8-layer module, simply because there’s more copper to trace.
- Trace and space geometry. 0.075 mm lines with 0.075 mm spacing need higher magnification and slower, more careful work than 0.2 mm lines.
- BGA and via-in-pad. Fine-pitch BGA breakout regions are the densest part of any board. Confirming which pad connects to which inner layer usually needs X-ray as well as optical imaging.
- Blind and buried vias. HDI stackups with microvias between specific layer pairs need the drill map reconstructed per span, not as a single through-hole set.
- Deliverable set. Gerbers and a drill file are one price. Gerbers plus a verified netlist plus a full schematic plus a costed BOM is a different price, because schematic capture is human interpretation work, not imaging work.
- Component identification. Sanded-off markings, house-numbered parts, and custom magnetics all add investigation time.
- Firmware. If the board has a programmed MCU and you need the code, that’s a separate workstream with its own feasibility question.
How long a multilayer board really takes
Lead time and cost don’t scale together perfectly. Imaging can be parallelized across engineers; schematic interpretation mostly can’t, because one person has to hold the whole circuit in their head. So a board with 800 components and 6 layers may cost less than a 12-layer board but take longer to deliver a clean schematic.
Rough shape of it, assuming a healthy sample and no firmware work:
| Board class | Relative cost | Relative lead time | What dominates |
|---|---|---|---|
| 2-layer, through-hole and simple SMD | Baseline | Shortest | Optical scan and continuity checks |
| 4-layer, mostly power/ground inner layers | Low multiple of baseline | Short | Delamination plus plane reconstruction |
| 6–8 layer with signal inner layers | Moderate | Medium | Layer-by-layer imaging, via alignment |
| 10–16 layer with BGAs | High | Long | X-ray, BGA net mapping, impedance notes |
| HDI / blind-buried via / rigid-flex | Highest | Longest | Per-span drill reconstruction, stackup verification |
Two practical accelerators: send more than one board, and tell us early which deliverables you don’t need. A second sample lets imaging and electrical verification run at the same time instead of in sequence, and it gives us a fallback if the first sample delaminates badly. Dropping a full schematic from the scope when you only need to fabricate can cut the timeline substantially. If schedule is the constraint, say so up front — that’s the whole point of a rapid PCB reverse engineering arrangement, and it changes how the job is staffed rather than how carefully it’s done.
What happens to your board in the lab
Order matters here, because doing steps out of sequence destroys information you can’t get back.
- Intake and documentation. High-resolution scans of both assembled sides, dimensional measurement, photos of every component marking, and notes on connectors, mounting holes, and keep-out areas.
- X-ray, before anything is removed. This shows internal via structure, BGA ball integrity, and buried features while the board is still intact.
- Electrical mapping. Continuity, resistance, and diode checks on the live assembly. This is the reference truth the reconstructed netlist gets compared against later.
- Component removal. Parts come off with controlled heat, are bagged and labeled by location, and the bare board is cleaned.
- Outer layer imaging. Solder mask and silkscreen captured, then removed so the copper can be scanned cleanly.
- Layer separation. The stackup is opened up one layer at a time. Each copper layer is scanned at magnification and dimensionally referenced to fiducials or tooling holes.
- Stackup measurement. Dielectric thicknesses, copper weights, and material type recorded — this is what lets a fab reproduce impedance on a controlled-impedance board.
- CAD reconstruction. Layers are aligned, vias tied together, and pads and traces rebuilt as real objects rather than traced images. Design rules get checked against IPC-2221 spacing conventions and trace widths sanity-checked against IPC-2152 for the currents involved.
- Verification. The extracted netlist is compared node by node against the electrical map from step 3. Discrepancies get re-imaged, not guessed at.
If a fabricated board is part of the deal, first articles are inspected against IPC-A-600 workmanship criteria and IPC-6012 performance classes before assembly, and the assembled unit is bench-tested against the original where a test setup exists. Our full PCB reverse engineering service can stop at files or carry through to a working assembled board — the choice affects the quote significantly.
What to send us for a real quote
Most quote requests we can’t price are missing the same three things. Send these and you’ll usually get a feasibility answer, a lead time, and a price without a back-and-forth:
- Clear photos of both sides of the board, on a dark, non-reflective background, whole board in frame, in focus, taken straight on rather than at an angle.
- Board dimensions — outline size and thickness. Thickness plus layer count tells us a lot about the stackup.
- Close-ups of the main chip markings, including any house numbers or laser-etched codes. If the markings have been removed, tell us.
- One line on deliverables: Gerbers and drill only, or Gerbers plus BOM, or full schematic, or a fabricated and assembled board.
- Layer count if you know it, plus anything you know about the original stackup, controlled impedance requirements, or connector part numbers.
- How many samples you can send, and whether any need to come back. On multilayer work, at least one sample is normally consumed.
What comes back: whether the board is feasible, whether it’s feasible at the deliverable level you asked for, a lead time range, and a price. If something looks risky, we say so before you ship — not after.
Where multilayer reverse engineering gets hard, and where it stops
These are the cases that cause trouble, and it’s better to know before you commit budget.
Harder than average
Buried resistors and embedded passives. Some boards carry resistive material inside the stackup. Once you grind through it, the value is gone. It has to be measured in-circuit first and inferred, which introduces tolerance uncertainty.
Heavy copper on inner layers. Delamination behaves differently when a 3 oz plane is bonded between thin dielectrics; the separation is messier and imaging needs more cleanup.
Rigid-flex and stiffened flex. Adhesive layers and coverlay complicate separation, and the flex sections deform during processing, which hurts dimensional accuracy.
Conformal coating and potting. Coating can usually be removed. Hard epoxy potting over a multilayer assembly sometimes can’t be removed without destroying the traces underneath, and we’ll tell you if the sample looks that way.
Sometimes not feasible
Badly corroded or fire-damaged boards where the copper itself has degraded — you can’t recover a net that’s physically gone. Single damaged samples of very dense boards, where there’s no second board to verify against. And RF boards where performance depends on material properties we can identify but not perfectly guarantee: we can reproduce the geometry and give you the measured stackup, but exact Dk/Df matching depends on what laminate is still available.
On the firmware side, honesty matters more. Whether a programmed MCU on your board can be read depends entirely on the part and how it was locked — STM32 parts at RDP Level 1 behave very differently from Level 2, MSP430 devices with a blown JTAG fuse and no BSL password are a different problem again, and lock bits on 8051 and AVR parts vary by generation. Nobody can promise a specific
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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