ODB++ Generation: How This Step Actually Works

ODB++ generation is the step where the recovered board data — copper per layer, drill and via structures, pad stacks, nets, component placement and the BOM reference — gets written into a single ODB++ database instead of a folder of separate Gerber, drill and pick-and-place files. The output is a directory tree (or a compressed .tgz) that your fab and assembly house can open as one intelligent dataset. It matters because ODB++ carries netlist and component intelligence that plain RS-274X does not.

If you’re getting quotes for a board copy and the shop keeps saying “we’ll send Gerbers,” this page is the difference you’re asking about.

What actually lives inside an ODB++ database

ODB++ is not a file format in the way Gerber is. It’s a structured folder hierarchy, and knowing the structure tells you what your fab can and can’t do with it.

• steps/ — each “step” is a panel or a single board. A production panel with 6-up placement and coupons lives here as its own step, referencing the single-board step.
• layers/ — one directory per layer, including copper, soldermask, silkscreen, paste, drill and rout. Each has a features file describing lines, pads, arcs and surfaces with real width and shape data, not just flashed apertures.
• netlists/ — the extracted net connectivity, which is what lets CAM compare “what the copper says” against “what the design says.” This is the part Gerber has no equivalent for.
• eda/data — component packages, pin-to-net mapping, reference designators, and top/bottom side assignment.
• matrix — layer order and stackup context. Gets the inner layers in the right sequence so nobody images L3 where L4 belongs.

That netlist directory is the reason experienced CAM engineers ask for ODB++. When they run a netlist compare and the copper matches the declared nets, a whole class of reverse-engineering error gets caught before any laminate is exposed.

ODB++ compared with the alternatives

We generate whichever your supply chain actually reads. Asking your fab first saves a round trip — some CAM departments still prefer Gerber plus an IPC-D-356 netlist and will convert anything else back down anyway.

How we build ODB++ from a physical board, in order

ODB++ generation is not a conversion button pressed at the end. The database is only as good as the layer data feeding it, so the sequence matters.

1. Intake and imaging. Outer layers are scanned or photographed at high resolution with the board flat and evenly lit. Board outline and mechanical features get measured with calipers or an optical comparator, not estimated from the image scale.
2. Component identification. Every marking is read, cross-referenced and recorded with its reference designator, package and orientation before anything is removed. This is what later populates the eda/data component records. Our full workflow for recovering a board layer by layer covers this stage in more depth.
3. Drill and via mapping. Hole sizes are measured with pin gauges or measured optically, then classified: plated through, non-plated, blind, buried, microvia. Blind and buried structures usually need X-ray to confirm which layer pair they span.
4. Layer separation. For multilayer boards, the stackup is opened up one layer at a time and each inner copper image is captured. Dielectric thicknesses are measured on a cross-section coupon where impedance matters.
5. Vectorization. Bitmap copper becomes real geometry — traces with actual widths, pads with actual shapes, polygons as surfaces. This is the slow part, and it’s where an experienced operator beats an auto-trace algorithm every time.
6. Netlist extraction and reconciliation. Connectivity is pulled from the vectorized layers and checked against continuity measurements taken on the physical board. Any net where the two disagree gets re-probed, not averaged.
7. Database assembly and DFM check. Layers, matrix, netlist and component data are written into the ODB++ structure, then run through CAM checks: annular ring, minimum trace and space, soldermask clearance, silkscreen over pad. Findings are reported against IPC-A-600 and IPC-6012 class expectations so you know whether the original was built to Class 2 or Class 3.

Step 6 is the one clients underestimate. Optical extraction alone will happily merge two nets that pass under a large ground pour, and only continuity testing on the real board catches it.

What we need from you before we can quote

Feasibility and price for ODB++ generation come down to a handful of facts. Send these and you’ll get a straight answer rather than a range wide enough to be useless.

• Clear photos of both sides, whole board in frame, on a dark non-reflective background, sharp enough to read component markings.
• Board dimensions — length, width and overall thickness. Thickness plus layer count tells us a lot about the stackup before we ever open it.
• Layer count if you know it, or say you don’t. We can determine it, but knowing up front sharpens the estimate.
• The marking on the main controller or FPGA, photographed straight on. Fine-pitch BGA under that part changes the effort meaningfully.
• One line on deliverables: ODB++ only, or ODB++ plus schematic, plus BOM, plus assembly files.
• Quantity of samples available. Layer separation is destructive. One board means one attempt.

What comes back is a feasibility assessment, a lead time, and a price. If we see something in your photos that will cause trouble — potting compound, a conformal coating, sanded-off part markings — you hear about it in that first reply, not three weeks in.

What drives the price and the schedule

There’s no flat rate, and any shop quoting one before seeing the board is guessing. The real drivers:

Layer count and density. A two-layer control board is a straightforward job. A ten-layer board with a 0.65 mm pitch BGA requires each inner layer imaged and vectorized separately, and the vectorization time doesn’t scale linearly with layer count — it scales with feature count.

Via architecture. Through-hole only is simple. Blind, buried and stacked microvias in an HDI stackup mean X-ray work plus careful correlation between layer pairs, and this is where schedules stretch.

Board condition. A clean working board is best. A field-returned board with burnt traces, corrosion or a missing corner needs interpolation, and every interpolated feature is an assumption you should be told about. Potted or epoxy-encapsulated assemblies are sometimes not recoverable at all without destroying the exact area you need.

Deliverable set. ODB++ alone is less work than ODB++ with a full hierarchical schematic and a sourced BOM. The tradeoffs are laid out in our breakdown of what drives reverse engineering cost.

Whether firmware is involved. Board data and code are separate jobs on separate timelines. If a locked MCU is part of the project, feasibility there is its own question — see how firmware recovery from a protected MCU works.

Honest limits of ODB++ generation

Some things the format simply cannot give you, and some boards fight back.

ODB++ is manufacturing data, not design intent. It tells the fab where copper goes. It does not tell you why the designer used 8 mil traces on that rail, what the target impedance was, or which net was deliberately routed away from the switcher. If you plan to modify the board, you want a schematic alongside it. Trace current capability can be sanity-checked against IPC-2152 once widths and copper weight are known, but that’s an inference, not recovered intent.

Dielectric material is measurable but not certain. We can measure thickness and estimate Dk from impedance measurements. Naming the exact laminate grade the original manufacturer bought is often not possible. For controlled-impedance RF boards, that gap is real and we say so.

Heavily damaged or ambiguous areas get flagged, not fudged. If a via barrel is destroyed and we cannot confirm which inner layer it landed on, that appears in the report as an open question. A database that looks complete but hides a guess is worse than one that admits the gap.

Flex and rigid-flex are harder. Thin polyimide layers delaminate unpredictably during separation, and the bend regions carry mechanical requirements that no CAM database records.

Very old boards can be easier than expected. Wide traces, generous spacing, through-hole only. A 1990s industrial controller often comes out cleaner than a modern six-layer consumer board of the same size.

On rights: we work on the assumption that you hold the rights to the design or have a legitimate maintenance, obsolescence or failure-analysis reason for the work, and that responsibility for IP compliance sits with you. Every project runs under NDA,

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