Why PCB Copy Accuracy Is the Only Metric That Matters
A copied PCB is worthless if it does not behave like the original. The entire point of board-level reverse engineering and duplication is to produce a file set—Gerber, drill, BOM, schematic—that yields a board electrically and mechanically identical to the sample. PCB copy accuracy is the umbrella term for every measurement, test, and comparison that proves the copy meets that goal.
Accuracy is not a single number. It is a stack of pass/fail gates spread across geometry, connectivity, impedance, component placement, and final function. Miss any one gate and the copy fails, even if the other gates look perfect. This article walks through each gate in the order a professional lab applies them, explains the tolerances involved, and shows you how to read a verification report when one lands on your desk.
Stage 1: Dimensional and Layer-Image Accuracy
Optical Scanning and Overlay Comparison
The first accuracy check happens the moment inner-layer images are captured. After stripping solder mask and copper from each layer—either chemically or by micro-sectioning—the lab photographs every layer at high resolution (typically 1200–2400 DPI or better). The resulting bitmap is vectorized into Gerber data, and that data is overlaid on top of the original scan.
- Pad position tolerance: ±0.5 mil (0.0127 mm) for standard boards; ±0.2 mil for BGA-class fanouts.
- Trace width tolerance: ±0.3 mil for impedance-critical traces; ±0.5 mil for general routing.
- Board outline tolerance: ±2 mil on overall dimensions; ±1 mil on slot and cutout features.
Any deviation outside these windows gets flagged and corrected before the data moves to the next stage. For high-layer-count boards like a 10-layer PCB copy, this overlay step is repeated for every individual copper layer, because registration drift between layers can accumulate and shift via-pad alignment.
Drill and Via Accuracy
Drill files are verified against the physical board using a measuring microscope or X-ray. The lab checks:
- Hole diameter (±0.5 mil for PTH, ±0.2 mil for micro-via).
- Hole-to-pad concentricity (annular ring must meet IPC-6012 Class 2 or Class 3).
- Blind and buried via start/stop layers (incorrect assignment here can create an open or short on fabrication).
This is especially critical on boards with sequential lamination. A 12-layer board with buried vias can have three or four drill sets, and each must map to the correct layer pair.
Stage 2: Netlist Extraction and Comparison
Geometry alone does not guarantee connectivity. Two traces can look correct on a scan yet connect to the wrong net because a via assignment was misread during delayering. This is why netlist extraction is a non-negotiable accuracy gate.
How the Netlist Is Built
The lab’s CAD tool traces every copper feature on every layer, follows vias between layers, and builds a net list—a table that says “pad A on component U3 connects to pad B on component R17 through these vias and traces.” This extracted netlist is then compared against one of two references:
- Schematic-derived netlist: If the lab has also reverse-engineered the PCB to a schematic, the schematic’s own netlist serves as the golden reference. A mismatch means either the schematic or the layout (or both) has an error.
- Continuity-tested netlist: A flying-probe or bed-of-nails tester probes every net on the physical board and records actual connectivity. This is the most trustworthy reference because it reflects what the board actually does, not what a drawing says it should do.
What a Mismatch Looks Like
Common netlist mismatches include:
| Mismatch Type | Typical Cause | Risk If Missed |
|---|---|---|
| Extra net (short) | Two traces merged during vectorization | Component damage or functional failure |
| Missing net (open) | Thin trace lost during chemical stripping | Signal path broken; board non-functional |
| Net swap | Via assigned to wrong layer pair | Signals routed to wrong pins; subtle malfunction |
| Split net | Power plane pour not fully reconstructed | Voltage rail has high impedance or dropout |
A professional lab resolves every mismatch before moving to fabrication. If you are working without an original schematic or BOM, the continuity-tested netlist becomes even more important because there is no design-intent document to fall back on.
Stage 3: Impedance and Stackup Verification
For any board carrying high-speed digital signals, RF traces, or differential pairs, dimensional accuracy and correct connectivity are necessary but not sufficient. The copy must also reproduce the characteristic impedance of controlled traces.
How Impedance Is Recovered
The lab measures the original board’s stackup—layer-to-layer dielectric thickness, copper weight, and prepreg/core material—using cross-section microscopy. These physical measurements feed into an impedance calculator (often a 2D field solver) to determine what impedance the original designer targeted. The copied Gerber and fabrication notes are then checked to confirm they will produce the same impedance on the same fab process.
Typical controlled-impedance tolerances are ±10 % for single-ended traces and ±10 % for differential pairs, matching IPC-6012 Class 2. Tighter tolerances (±5 %) are achievable but require the fab house to run test coupons. For a deeper dive, see our guide on impedance-controlled PCB copy.
Stackup Documentation
The verification report should include a stackup drawing that lists:
- Each copper layer and its weight (e.g., 1 oz, 0.5 oz).
- Each dielectric layer, its material (FR-4, Rogers, polyimide), and its measured thickness.
- Calculated impedance for every controlled trace class.
- The fab house’s target impedance and coupon test plan.
Stage 4: BOM and Component-Placement Accuracy
A board is more than bare copper. The BOM (bill of materials) and the pick-and-place file must be accurate, or the assembled copy will not work.
BOM Verification Methods
- Visual identification: Reading part markings under magnification.
- Measurement: Checking passive values with an LCR meter after desoldering.
- Cross-reference: Matching identified part numbers against distributor datasheets to confirm package, value, and voltage rating.
- Functional inference: When markings are absent or sanded off, the lab infers the part from its circuit context (e.g., a 0402 resistor between a regulator’s feedback pin and ground is likely a specific value dictated by the regulator’s datasheet).
Placement Accuracy
The pick-and-place file specifies X-Y coordinates, rotation, and side (top or bottom) for every component. Accuracy here is typically ±2 mil for fine-pitch parts and ±5 mil for standard SMD. BGA escape routing demands even tighter placement accuracy, which is why BGA board copy projects receive extra attention during this stage.
Stage 5: Fabrication and Assembly of the Verification Sample
Once the file set passes all digital checks, the lab orders a small batch—often just one to three boards—from a qualified PCB fabricator. These boards are assembled with the verified BOM and undergo incoming inspection:
- Bare-board electrical test: Flying-probe or fixture test confirms every net is connected and no shorts exist.
- Solder-paste inspection (SPI): Ensures paste volume is correct before reflow.
- Automated optical inspection (AOI): Checks solder joints, tombstoning, and missing components after reflow.
- X-ray inspection: Mandatory for BGA and QFN packages where joints are hidden beneath the component body.
Stage 6: Powered Bring-Up and Golden-Board Compare
The ultimate accuracy test is functional. The copied board is powered up and its behavior is compared against the original—the “golden board.”
What Gets Measured
| Parameter | Method | Acceptable Deviation |
|---|---|---|
| Supply rail voltages | Multimeter / oscilloscope at test points | ±1 % of nominal |
| Clock frequencies | Frequency counter or spectrum analyzer | ±50 ppm (crystal-dependent) |
| Signal integrity (eye diagram) | High-bandwidth oscilloscope | Eye opening ≥ original board’s margin |
| Current draw (idle and loaded) | Bench supply with current readout | ±5 % of original |
| Thermal profile | IR camera | No hot spot > 5 °C above original |
| Communication interfaces | Protocol analyzer (UART, SPI, I²C, Ethernet) | Zero frame errors over test duration |
For a comprehensive look at this final stage, read our article on continuity testing, ICT, powered bring-up, and golden-board comparison.
When the Copy Fails Bring-Up
A failure at this stage does not necessarily mean the layout is wrong. Common root causes include:
- A BOM substitution that changed a critical timing component.
- A stackup variation from the fab house that shifted impedance out of range.
- A firmware-locked MCU whose code could not be extracted (the board is electrically correct but has no program to run).
Each root cause is traced, corrected, and the board is re-tested until it matches the golden board within the tolerances listed above.
How to Read a Verification Report
A credible lab delivers a verification report alongside the file set. Here is what to look for:
- Layer-by-layer overlay images showing the scan versus the Gerber, with deviation heat maps.
- Netlist comparison log listing total nets, matched nets, and resolved mismatches.
- Impedance calculation sheet with measured stackup values and solver output.
- BOM with sourcing notes—exact part numbers, acceptable alternates, and any parts that could not be identified.
- Functional test log with oscilloscope screenshots, voltage readings, and pass/fail summary.
If any section is missing, ask for it. A lab that skips documentation is a lab that may have skipped the test itself. You can learn more about our own reverse-engineering process and capabilities on our about page.
Factors That Make PCB Copy Accuracy Harder
Not every board is equally easy to verify. Several factors push accuracy risk higher:
- High layer count: More layers mean more delayering steps and more chances for registration error.
- Blind and buried vias: These cannot be probed from the surface, so X-ray and cross-section are the only verification paths.
- Flex and rigid-flex construction: Material properties differ from standard FR-4, affecting impedance calculations.
- Sanded or coated component markings: Forces the lab to infer BOM values, adding uncertainty.
- Single-sample projects: If the original board is the only one available, destructive delayering means there is no second chance—every step must be right the first time.
What You Can Do as a Buyer to Improve Accuracy
Even if you have no documentation at all, you can still help the lab deliver higher PCB copy accuracy:
- Provide a working board so the lab can perform golden-board comparison.
- Provide a second board (even a dead one) so one can be used for destructive analysis while the other serves as a reference.
- Share any partial documentation—even a hand-drawn block diagram or a photo of the label with a part number helps.
- Specify your end-use environment (temperature range, vibration, compliance standards) so the lab can choose appropriate fabrication classes.
- Clarify legal ownership upfront to avoid project delays. Understanding the legal boundaries of board duplication before you start saves time for everyone.
Accuracy Is a Process, Not a Promise
No single test proves a copied PCB is accurate. Accuracy emerges from a disciplined chain of checks—dimensional overlay, netlist comparison, impedance verification, BOM validation, bare-board electrical test, and powered functional comparison. Skip a link in that chain and you risk shipping boards that look right but fail in the field.
When evaluating a reverse-engineering partner, ask to see a sample verification report from a past project (with client data redacted). The depth and clarity of that report will tell you more about the lab’s commitment to PCB copy accuracy than any marketing claim ever could.
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