PCB Copy Accuracy: What It Means and How We Verify It

PCB copy accuracy is the degree to which a reverse-engineered board’s Gerber files, BOM, netlist, and stackup reproduce the electrical and mechanical behavior of the original. A copy is considered accurate when every trace, via, pad, and drill falls within IPC Class 2 or Class 3 tolerances—typically ±0.5 mil (0.0127 mm) for trace width and ±2 mil (0.05 mm) for drill placement—and the assembled board passes functional test against the original’s performance baseline. Accuracy is not binary; it is a stack of individual measurements, each with its own pass/fail threshold.

Why PCB Copy Accuracy Is Harder Than It Sounds

A PCB is not a photograph. Copying the copper pattern is only the start. The original board carries implicit information—stackup dielectric constants, impedance targets, solder-mask dam widths, annular ring margins—that never appears on a silkscreen or in a visible trace. When any of these parameters drift outside tolerance, the copy may etch cleanly but fail electrically under load, at temperature, or at frequency.

Our engineers see three recurring accuracy failures in boards that arrive for a second opinion after another shop’s attempt:

• Net-short from merged pads: Optical capture at low DPI merges two adjacent 6-mil pads into one blob. The Gerber looks fine on screen; the fab creates a bridge.
• Impedance miss on differential pairs: Trace width is correct, but the dielectric thickness in the new stackup is 1 mil off. A 100 Ω differential pair lands at 92 Ω—enough to cause USB 3.0 eye-diagram failures.
• Drill-to-copper clearance violation: Via placement is 1.5 mil off center, violating the 5-mil annular ring rule for IPC Class 3. The board passes bare-board test but develops barrel cracks after thermal cycling.

These are not edge cases. They are the normal failure modes when accuracy verification is skipped or done only visually.

What Tolerances Define an Accurate PCB Copy?

The table below lists the parameters we measure on every copy project and the tolerance bands we hold to. These align with IPC-2221B and IPC-6012D Class 2/3 requirements.

When a board carries impedance-controlled differential pairs, we reconstruct the stackup using cross-sectioned dielectric measurements and run a 2D field solver before releasing Gerbers. Without that step, hitting ±8% impedance on a copy is largely luck.

How We Verify PCB Copy Accuracy: Step by Step

1. Pre-Scan Baseline

Before any layer is stripped, we photograph the original board at 2400 DPI minimum, record total dimensions with a calibrated CMM, and run a flying-probe continuity/isolation test to establish the “known-good” netlist. This baseline is the reference every subsequent check points back to.

2. Layer-by-Layer Extraction and Overlay

Each copper layer is imaged after chemical de-lamination (or micro-sectioned for HDI boards with blind and buried vias). The extracted bitmap is vectorized into Gerber RS-274X, then overlaid pixel-for-pixel against the original scan. Our software flags any deviation exceeding 0.3 mil—well below the Class 3 threshold—so an engineer can decide whether the delta is a real discrepancy or an artifact of etch irregularity on the original.

3. Netlist Comparison

We export a netlist from the reconstructed Gerber set and diff it against the baseline flying-probe netlist. A single missing net or unexpected short stops the project until the root cause is found. This step catches roughly 12–15% of errors that survive visual overlay, particularly on dense BGA breakouts where two vias can swap positions without changing the visual pattern much.

4. DRC Against IPC Rules

Design Rule Check runs against the tolerance table above. Violations are logged, reviewed, and corrected. On legacy boards (pre-2005 era), the original itself sometimes violates modern IPC rules; in those cases, we flag the violation and let the client decide whether to replicate it or upgrade it.

5. Prototype Fabrication and Electrical Test

The first fabricated panel undergoes bare-board e-test (flying probe or fixture, depending on volume) and, for impedance-controlled boards, TDR coupon measurement. Our first article inspection report documents every measured parameter against the tolerance spec. Only after FAI sign-off do we release files for production.

For a deeper look at the full verification chain, see our accuracy verification workflow.

What Degrades Accuracy—and How to Prevent It

Source Board Condition

An original board with corroded traces, lifted pads, or inner-layer delamination forces the engineer to reconstruct missing geometry from context—net connectivity, component datasheets, and adjacent routing patterns. Accuracy drops when more than 5–8% of a layer’s copper is damaged. Sending the cleanest available sample board is the single highest-leverage thing a client can do to improve copy accuracy.

Scan Resolution and Vectorization

Scanning at 1200 DPI is common but insufficient for boards with 3/3 mil trace/space. At 1200 DPI, one pixel equals roughly 0.85 mil—meaning a 3-mil trace is only 3.5 pixels wide. Sub-pixel errors during vectorization can shift a trace edge by nearly 30% of its width. We scan at 2400 DPI minimum, and 4800 DPI for HDI boards, specifically to keep vectorization error below 0.2 mil.

Stackup Reconstruction

Dielectric thickness matters for impedance, crosstalk, and power-plane capacitance. We micro-section the original board at three points (center, edge, and one corner) and measure each dielectric layer with a calibrated optical microscope. Typical measurement uncertainty is ±0.2 mil. Skipping this step—or assuming standard 1080/2116 prepreg without measuring—introduces 5–15% impedance error on controlled-impedance boards.

BOM Accuracy

A perfect Gerber set paired with wrong component values still fails. We cross-reference component markings against distributor databases and, where markings are worn, use LCR measurement or decap to confirm part identity. Boards with damaged or missing silkscreen require extra BOM verification time, but skipping it is the fastest path to a non-functional copy.

Accuracy Expectations by Board Complexity

“Accuracy expectation” here means the percentage of nets that pass continuity/isolation on the first prototype run. The remaining fraction is almost always fixable in one Gerber revision—typically a pad size tweak or clearance adjustment, not a fundamental layout error.

How Accurate Does Your Copy Actually Need to Be?

Not every application demands Class 3. A replacement control board for industrial equipment running at 10 MHz may tolerate ±10% impedance variation and ±2 mil trace width error without any functional impact. A 10 Gbps SerDes backplane will not. Before starting a copy project, define your pass/fail criteria: what signals are impedance-sensitive, what thermal margins exist, and what regulatory or qualification testing the copy must survive. This scoping step prevents over-engineering simple boards and under-engineering critical ones.

If you are evaluating whether a copy project is feasible for your board, request a project estimate with photos and we will return a realistic accuracy assessment within one business day.

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