PCB Copy Deliverables | What You Actually Receive

What Are PCB Copy Deliverables?

PCB copy deliverables are the complete set of engineering files—Gerber/ODB++ fabrication data, schematic diagrams, bill of materials, netlist, drill files, and (where applicable) extracted firmware—handed to you after a board has been reverse-engineered. Every file is production-ready: you can send the package directly to a fabricator and assembler without additional CAD work. The exact scope depends on board complexity, but the core file set described below is standard for every project we complete.

Why the Deliverable Package Matters More Than the “Copy”

Many engineers fixate on whether a copy is “accurate” without asking what they will physically receive at the end. A pixel-perfect image of copper layers is useless if it lacks drill data, impedance notes, or a verified BOM. The PCB copy deliverables define whether you can actually manufacture, test, and maintain the board long-term.

Our engineers treat the deliverable package as the product—not the cloned board itself. A cloned board is a verification step; the files are the asset. Below is every item in a standard delivery, with formats, tolerances, and the verification method behind each.

Complete PCB Copy Deliverables Checklist

How Each Deliverable Is Created and Verified

Gerber and Drill Files

Copper layers are captured through high-resolution optical scanning (1200–2400 DPI) and, for multilayer boards, controlled layer-by-layer delamination. Inner layers are photographed, digitized, and reconstructed in CAD. Every Gerber layer is DRC-checked against IPC-2221 design rules before export. For boards with 6+ layers, our multilayer and HDI layout copy workflow includes X-ray cross-section imaging to confirm via stacks and buried structures.

Drill files are generated from the same CAD model. Plated through-holes, non-plated holes, blind vias, and back-drilled stubs are each assigned separate tool codes per IPC-NC-349. Hole diameters are measured with pin gauges or optical comparators to ±0.05 mm.

Stackup and Impedance Data

We cross-section at least two locations on the donor board to measure dielectric thickness, copper weight, and prepreg/core arrangement. This data feeds into a stackup table that your fabricator can quote directly. Controlled-impedance nets get a TDR measurement on the donor board, and the reconstructed stackup is tuned in a 2D field solver until simulated impedance matches within ±5 Ω. For more on this process, see our controlled-impedance trace recovery documentation.

Schematic Diagram

The schematic is reverse-engineered from the physical board—not auto-generated from a netlist dump. Our engineers trace signal flow, identify functional blocks, and annotate power rails, decoupling strategy, and interface buses. The result is a human-readable, hierarchical schematic you can use for debugging, modification, or redesign. Net names follow the IC datasheet conventions where identifiable (e.g., SPI_CLK, UART_TX).

Schematics are delivered in both PDF and editable native CAD format. If you need a specific EDA tool (Altium, KiCad, OrCAD, PADS), state it at project kickoff.

Bill of Materials

Every component is identified by visual inspection, marking decode, and—where markings are absent or ambiguous—LCR measurement and X-ray inspection. The BOM includes:

• Manufacturer part number (MPN) with at least one verified alternate
• Package footprint (e.g., 0402, QFP-64, BGA-256)
• Quantity per board
• Distributor stock status flag (checked against Digi-Key/Mouser/LCSC at time of delivery)

Obsolete parts are flagged with a recommended replacement and any required footprint or schematic change. This is critical for legacy boards where 30–40 % of passives may have shifted to NRND status.

Firmware and EEPROM Images

Firmware extraction is only performed when you provide proof of IP ownership or authorized maintenance rights. Images are read via JTAG, SWD, ISP, or chip-decap methods depending on the MCU protection level. Every image is SHA-256 checksummed and delivered alongside a read log. If the MCU is read-protected and decryption is not feasible, we document the limitation upfront—no surprises after payment.

What Determines the Scope of Your PCB Copy Deliverables?

Not every project produces every item in the table above. Three factors control scope:

• Board complexity: A 2-layer FR-4 board may not need impedance notes. A 12-layer HDI board with blind/buried vias will include a full stackup report, impedance table, and via-structure map.
• Project goal: If you only need fabrication files for a replacement run, we can skip the schematic. If you need to redesign, the schematic and native CAD source are essential.
• Firmware presence: Boards with no programmable ICs skip the firmware deliverable entirely.

We define the deliverable scope in writing before work begins. You can review a full deliverable set documentation page for the expanded reverse-engineering package, which adds test-point maps and functional block diagrams.

How PCB Copy Deliverables Compare Across Service Tiers

The Fabrication-Only package is the minimum needed to manufacture a replacement board. The Full Copy package adds the schematic and firmware for maintenance and debugging. The Copy + Redesign package gives you editable CAD source so your team can modify the design. Pricing scales accordingly—see our guide to realistic PCB copy costs for typical ranges.

What Can Go Wrong With Deliverables—and How We Prevent It

Common failure modes in PCB copy deliverables from less rigorous providers:

• Missing inner-layer data: Some shops skip controlled delamination and guess inner layers from via positions. We photograph every inner layer at 2400 DPI and overlay against the original board.
• Unverified BOM: Auto-populated BOMs from OCR on component markings produce 5–15 % error rates on boards with remarked or house-numbered parts. We cross-check every IC against datasheet pin-count and function.
• No netlist verification: Without a bare-board continuity test against the IPC-D-356A netlist, open/short errors pass silently into production. Our prototype boards are electrically tested before file release.
• Impedance mismatch: Delivering Gerbers without stackup notes means your fabricator guesses dielectric thickness, and your 50 Ω USB traces come back at 62 Ω. We include measured stackup data and solver-verified trace geometry.

If the donor board has physical damage—burned traces, corroded vias, or inner-layer delamination—we document affected areas and reconstruct from redundant routing or circuit analysis. Damaged zones are flagged in the Gerber file notes so you know exactly where interpolation was used.

After You Receive Your PCB Copy Deliverables

With the file package in hand, your next steps typically follow one of three paths:

• Prototype verification: Send Gerbers and BOM to a fab/assembly house, build 3–5 units, and run functional tests. Our prototyping and board bring-up service handles this end-to-end if you prefer a single vendor.
• Volume production: Once the prototype passes, move to scaled manufacturing runs using the same verified files.
• Design modification: Open the native CAD source, swap obsolete parts, add features, and re-export updated Gerbers for your next revision.

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