The PCB copy process turns a physical board into a manufacturable file set: scanned and separated copper layers, a rebuilt Gerber and drill package, a bill of materials, and — if you ask for it — a schematic and a working sample. It runs in five stages: intake and imaging, layer separation, component identification, file rebuild, then verification against the original. Most of the elapsed time goes into the last two.
This page walks the stages in order, tells you what we need from you before we can quote, and names the cases that get hard.
Stage 1: what happens to your board in the first day
The board arrives and gets photographed exactly as received, both sides, before anyone touches it. That “as-received” record matters later when you ask whether a missing capacitor was your fault or ours.
Then we log the physical facts: overall dimensions, board thickness with a micrometer, copper weight estimate, finish (HASL, ENIG, immersion silver), solder mask and silkscreen color, and the mechanical outline including every mounting hole and cutout. Connector positions get measured against a datum edge, not against each other, so cumulative error doesn’t creep in.
Next comes high-resolution scanning of both outer layers. We shoot at a resolution fine enough to resolve the narrowest trace and the smallest annular ring on the board, and we scan with a known dimensional reference in frame so the image scale is provable rather than assumed. Warped boards get flattened under glass. Conformal coating gets removed chemically in a small test area first, so we know how the coating reacts before we treat the whole board.
When the board goes to X-ray instead of the scanner
If the board has BGAs, QFNs, or blind and buried vias, optical scanning of the outer layers won’t tell you where the connections go. That’s when we shoot it with X-ray imaging before any layer is removed — via structure, buried via depth, and BGA ball layout all show up while the board is still intact. Doing this first is not optional on HDI work, because once you start grinding you cannot go back and ask the question again.
Stage 2: separating the inner layers without losing data
A two-layer board needs no separation. Everything is visible from the top and bottom, and the whole job is scanning, tracing, and checking.
Four layers and above is a different exercise. The outer copper is imaged first, then material is removed a layer at a time — controlled grinding or chemical delamination depending on the laminate — and each newly exposed copper layer is scanned before the next one is touched. This is destructive. Your sample board does not come back in one piece, which is why we always ask whether you can send two.
The registration problem is what makes this skilled work. Every scanned layer has to be aligned to the same coordinate origin, usually a set of tooling holes or plated through-holes that pass through the full stack. Get the alignment wrong by a few thousandths and vias on layer 3 stop landing on pads on layer 2, which shows up as phantom open circuits in the netlist much later.
We also record the stackup itself: dielectric thicknesses between each copper layer, core versus prepreg arrangement, and copper thickness per layer. On impedance-controlled boards that data is the difference between a copy that works and a copy that looks right and fails at speed. A 50-ohm trace is 50 ohms because of its width and its distance to the reference plane — copy the width and guess the dielectric, and you’ve built something else.
Why layer count changes the schedule so much
| Board type | What drives the effort | Relative time |
|---|---|---|
| 2-layer, through-hole, coarse pitch | Scan, trace, verify. No separation. | Shortest |
| 4-layer with power/ground planes | Two inner layers to image and register; planes are easy to trace | Moderate |
| 6–8 layer with mixed signal routing | Every inner layer carries signals; more nets to verify | Noticeably longer |
| HDI, blind/buried vias, fine-pitch BGA | X-ray mapping, via-in-pad structures, microvia depth | Longest, and the highest risk of “not fully feasible” |
If you’re weighing whether your project sits in the easy half or the hard half of that table, the practical differences between two-layer and four-layer copy work are worth reading before you send the board.
Stage 3: identifying every component on the board
Layer data gives you copper. It doesn’t tell you what sits on top of it. Component identification runs in parallel with layer separation and is often the slowest single part of the job.
Marked parts are straightforward — the engineer reads the top marking under a microscope, checks the package, and matches it to a datasheet. The work is in the unmarked and ambiguous parts:
- Passives — resistors are read from markings where present, and measured in circuit or after removal where not. Capacitors need capacitance, voltage rating, and dielectric class; a 100nF X7R and a 100nF Y5V are not interchangeable in a timing or filter position.
- House-marked and laser-marked ICs — a custom marking means the part number has to be inferred from pinout, package, function in the circuit, and comparison against likely families.
- Magnetics — inductors and transformers get measured for inductance and DC resistance, and the winding structure documented where the part can be sectioned.
- Programmed devices — MCUs, EEPROMs, CPLDs. The part number is easy; the contents are a separate project entirely, which we cover further down.
Obsolete parts get flagged rather than silently substituted. If a linear regulator or optocoupler on your board went end-of-life six years ago, you need to know that during the copy, not after the first production run. The full workflow behind building a BOM from a physical board goes into how measured values get cross-checked.
Stage 4: rebuilding the files and proving they match
Now the data becomes a design. Scanned layers are vectorized into real copper geometry, pads become library footprints, and drill data is rebuilt with actual measured hole sizes separated into plated and non-plated. The output is a Gerber set (or ODB++/IPC-2581 if you prefer), a drill file, a stackup document, a fabrication drawing, and a BOM with reference designators.
Verification is the part that separates a copy you can build from a pile of images. Three checks matter:
- Netlist comparison. A netlist is extracted from the rebuilt files and compared, net by net, against continuity measured on the original board. Every discrepancy gets resolved by going back to the physical sample, not by picking whichever version looks nicer.
- Dimensional check. Board outline, mounting hole positions, and connector centers are measured against the original. Mechanical fit failures are the most expensive kind, because they only appear after you’ve paid for boards.
- DRC and fabrication review. The rebuilt files get checked for manufacturability against normal design rules — minimum annular ring, spacing, mask clearance — in the spirit of IPC-2221 design practice, and the fabricated result is inspected to IPC-A-600 and IPC-6012 class expectations for plating, annular ring, and conductor width.
If a schematic is part of your order, it gets drawn from the verified netlist rather than sketched from the layout, and it’s organized by function — power, MCU, analog front end — instead of mirroring the board’s physical arrangement. That step is closer to full reverse engineering than to straight duplication, and it costs more because it requires understanding the circuit, not just recording it.
Exactly what to send us, and what comes back
Quoting is fast when the intake is good. Send this:
- Clear photos of both sides, whole board in frame, on a dark non-reflective background, taken straight down with even light. No angled phone shots across a workbench.
- Board dimensions and thickness, even approximate.
- Layer count if you know it. If you don’t, say so — we can estimate from edge inspection.
- Close-up photos of the main IC markings, especially any MCU, memory, or programmable logic.
- One line on deliverables: Gerber only, Gerber plus BOM, add a schematic, add assembled samples.
- Whether you can supply two boards, and whether one may be destroyed.
Back from us: a feasibility assessment naming anything we can’t fully recover, a deliverable list, a lead time, and a price. If something on the board looks like a problem — potting compound, a house-marked ASIC, an unreadable programmed device — we tell you before you ship, not after. Pricing tracks layer count, board area, component count, BGA presence, whether firmware is involved, and how deep the deliverable set goes; there’s no flat rate that survives contact with a real board.
Where the PCB copy process runs into real limits
Copper geometry is recoverable. These things are not, or not always:
Programmed device contents. Gerbers and a BOM will get you a physically identical board that does nothing, because the code isn’t in the copper. Firmware recovery from a locked MCU is a separate service with its own feasibility question, which depends heavily on the part — STM32 RDP level, MSP430 JTAG fuse state, AVR and 8051 lock bit configuration all change the answer. We don’t promise any specific chip is readable until we’ve seen it.
Potted and epoxy-filled assemblies. Removing potting without destroying the traces underneath is possible sometimes and not others, and it depends on the compound.
Deliberately obscured parts. Sanded-off markings, custom silicon, and one-off ASICs may end up documented as “unidentified device, pinout recorded” rather than as a part number.
Damaged samples. Burned traces, corrosion, or a board that’s had three repairs done to it means some nets have to be reconstructed by inference. We mark those explicitly rather than pretending they’re
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