PCB Copy Sample Requirements | Condition, Quantity & Parts

What Are the PCB Copy Sample Requirements?

PCB copy sample requirements define the physical condition, quantity, completeness, and packaging standards your board must meet before a reverse-engineering lab can begin work. Sending a sample that fails any of these criteria adds days—sometimes weeks—to your timeline. The core requirements are: at least one functional or intact board, all components preferably still mounted, no deliberate damage to copper layers, and proper anti-static packaging. Meeting these requirements up front is the single fastest way to keep your project on schedule.

Why Sample Quality Determines Project Outcome

Every PCB copy project begins with the physical board. Our engineers use high-resolution optical scanning (down to 0.1 mil / 2.5 µm resolution) and controlled chemical delayering to capture each copper layer. If the sample is corroded, cracked through a via, or missing a critical section of copper, the data we extract is incomplete. Incomplete data means guesswork, and guesswork means errors in your Gerber files.

A clean, intact sample typically yields ≥ 99 % trace-routing accuracy on boards up to 8 layers. A damaged sample on the same board class can drop accuracy to 90–95 %, requiring additional verification cycles. You can read more about reverse-engineering accuracy and the factors that affect it in our dedicated guide.

Board Condition: What “Intact” Actually Means

We do not need a brand-new board. We need a board where every copper layer is readable. Here is what qualifies—and what does not:

If your board falls into the “Conditional” or “Risky” categories, upload clear photographs through our secure file transfer portal so we can evaluate feasibility at no charge before you ship anything.

How Many Boards Should You Send?

The minimum is one. But sending more dramatically improves results and protects against risk.

Recommended Quantities by Layer Count

For boards with four or more layers, the delayering process physically removes copper to expose inner layers. That means the first board is consumed. If you want us to also verify the copy against a working reference, you need at least one additional unit. Our guide on multilayer board copying and what changes with layer count explains the process in detail.

What If You Only Have One Board?

We work with single samples regularly. The trade-off is that post-copy functional comparison must rely on netlist checks and DRC rather than a side-by-side power-on test. For 1–2 layer boards this is a non-issue. For 6+ layer boards, the risk of a missed connection rises slightly—typically from < 0.5 % to about 1–2 %. We flag this in the project scope so you can decide whether to proceed or source a second unit.

Components: Mounted, Removed, or Desoldered?

Leave components mounted unless we tell you otherwise. Here is why:

• BOM extraction: Our technicians photograph and catalog every component—markings, packages, orientation—to generate an accurate bill of materials. Removing parts before shipping erases orientation data and risks losing small 0201/0402 passives.
• Pad preservation: Amateur desoldering with a heat gun often lifts pads or damages solder mask, especially on fine-pitch QFP and BGA footprints. Lifted pads create gaps in the netlist.
• IC identification: Some ICs have markings that wear off or become unreadable once removed. We photograph them in-situ under controlled lighting before any disassembly.

Exception: If a specific component is proprietary and you do not want it included in the copy scope, remove it yourself and note its location on a board photo. We will leave that footprint in the layout but exclude it from the BOM.

What to Include With Your Sample

The board alone is the minimum. But every additional piece of information you provide reduces turnaround. Use our preparation checklist as a packing reference, and include as many of these items as you have:

• Known schematic or partial schematic — even a hand-drawn block diagram helps engineers verify net connectivity faster. (And no, you do not need the original schematic for us to proceed.)
• Existing BOM or component list — speeds up parts identification, especially for house-marked or custom-labeled ICs.
• Photos of both sides — high-resolution phone photos (≥ 12 MP) taken under even lighting serve as a pre-shipping reference in case anything shifts during transit.
• Operating notes — input voltage, clock frequency, known firmware version, connector pinouts. These help our engineers validate the copy electrically.
• Special instructions — “Do not desolder U7,” “Layer 3 is a split power plane,” or “Board was potted; I’ve already removed the compound.”

Packaging and Shipping Your PCB Sample

Improper packaging is the most common—and most preventable—cause of sample damage. Follow these rules:

• Wrap the board in anti-static (ESD) bags. Regular plastic bags can generate static that damages sensitive ICs.
• Place the bagged board between two pieces of rigid cardboard or foam, at least 3 mm thick on each side.
• Fill remaining box space with bubble wrap or packing peanuts so the board cannot shift.
• For multilayer or flex boards, add a “FRAGILE — ELECTRONIC COMPONENTS” label.
• If shipping internationally, include a commercial invoice describing the item as “printed circuit board sample for engineering analysis, no commercial value” to streamline customs.

Our full packing and customs guide covers carrier selection, insurance, and country-specific documentation: how to send a PCB sample safely.

Common Mistakes That Delay Projects

After processing thousands of inbound samples, these are the issues we see most often:

• Sending a photograph instead of the board. Photos can help with initial quotes, but recovering a board from photographs alone has hard limits—inner layers are invisible, and trace widths cannot be measured to the required ± 0.5 mil tolerance.
• Removing BGA chips “to help.” BGA removal without proper rework equipment tears pads and redistributes solder, making footprint reconstruction difficult.
• Shipping without ESD protection. We have received boards in paper envelopes. One had a cracked FPGA that added $400 and five days to the project.
• Not disclosing board damage. If a section is burnt or missing, tell us up front. Surprises at intake trigger a re-quote and restart the timeline.

What Happens After We Receive Your Sample?

Once your board arrives at our lab, the workflow follows a defined sequence: intake inspection, high-res photography, component cataloging, layer-by-layer scanning or delayering, CAD tracing, netlist extraction, DRC, and final file packaging. The typical turnaround from receipt to deliverables ranges from 3 working days for a simple 2-layer board to 15–20 working days for a 12+ layer HDI design. Check our turnaround time breakdown for specifics by complexity class.

Quick-Reference: PCB Copy Sample Requirements Checklist

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