What Is PCB Duplication?
PCB duplication is the process of reverse-engineering a physical circuit board to produce a complete set of manufacturing files — Gerber data, drill files, a bill of materials (BOM), and often a schematic — so the board can be re-fabricated without the original design source. It is used when OEM files are lost, a vendor has gone out of business, or a legacy product needs continued production. Our engineers work from your sample board, not from assumptions, and the resulting file package is verified against the original before release.
Why Engineers Need PCB Duplication
The most common trigger is a discontinued product line where the original EDA files no longer exist. Other scenarios include:
- Vendor lock-in escape. Your contract manufacturer holds the design data and you need independent production capability.
- Legacy equipment support. Replacement boards for industrial, HVAC control systems, or telecom infrastructure that must stay in service for 15–25 years.
- Second-source qualification. A duplicate file set lets you qualify an alternate fabricator without re-designing from scratch.
- Post-failure forensics. Duplicating a failed board provides a baseline for root-cause analysis and redesign.
In each case, the deliverable is the same: a production-ready data package that any IPC-capable fab house can use.
How the PCB Duplication Process Works
Step 1 — Incoming Inspection and Photography
We photograph both sides of the bare or populated board at high resolution (≥1200 DPI optical scan), log board dimensions, and note any visible damage. If the board arrives populated, we catalog and cross-reference every component before de-soldering.
Step 2 — Layer-by-Layer Imaging
For multilayer boards, controlled chemical or mechanical de-lamination exposes each copper layer. Each layer is scanned, aligned to fiducials, and digitized. On a standard 4-layer FR-4 board this takes roughly one working day; a 14-layer design can require three to four days of careful sectioning. For boards above 14 layers — such as 20-layer telecom backplanes — X-ray micro-CT supplements destructive methods to capture via structures without losing registration.
Step 3 — Schematic Extraction
Netlist data from the digitized layers is combined with the BOM to reconstruct a hierarchical schematic. Our engineers verify net connectivity against the physical board using continuity testing on a second sample when available.
Step 4 — File Generation and DRC
Gerber RS-274X or Gerber X2 files, Excellon drill files, IPC-D-356 netlists, and a pick-and-place centroid file are generated. Every file set passes automated Design Rule Checks (DRC) calibrated to the original board’s fab class — typically IPC Class 2 or Class 3.
Step 5 — Verification Build
A prototype run (usually 3–5 pieces) is fabricated and electrically tested against the original. Only after functional verification do we release the final data package. You can request a sample duplication build to validate fit and function before committing to volume.
Deliverable File Formats
| Deliverable | Format | Notes |
|---|---|---|
| Copper layers | Gerber RS-274X / X2 | One file per layer; includes pour/fill data |
| Solder mask | Gerber RS-274X | Top and bottom |
| Silkscreen | Gerber RS-274X | Reconstructed from board markings |
| Drill data | Excellon (NC Drill) | Plated and non-plated separated |
| Netlist | IPC-D-356 / ODB++ | For bare-board electrical test |
| BOM | Excel / CSV | Mfr part number, value, package, quantity |
| Schematic | PDF + native (Altium/KiCad on request) | Hierarchical, net-annotated |
| Centroid / XY | CSV | For SMT pick-and-place |
| Stackup drawing | Material, thickness, copper weight per layer |
Tolerance and Accuracy Benchmarks
Accuracy in PCB duplication depends on the board’s complexity and condition. Here are realistic benchmarks our lab achieves:
| Parameter | Standard (≤6 layers) | Complex (8–16 layers) | High-density (≥18 layers) |
|---|---|---|---|
| Trace width accuracy | ±0.5 mil (±0.013 mm) | ±0.8 mil (±0.020 mm) | ±1.0 mil (±0.025 mm) |
| Via position accuracy | ±0.5 mil | ±1.0 mil | ±1.5 mil |
| Impedance match (controlled lines) | ±5 % | ±7 % | ±10 % (re-simulated) |
| BOM identification rate | ≥98 % | ≥95 % | ≥92 % (obsolete parts flagged) |
| Typical turnaround | 5–7 working days | 8–12 working days | 12–20 working days |
Boards with blind/buried vias, sequential lamination, or embedded passives push toward the longer end of these ranges. RF and microwave boards require additional impedance re-simulation — our RF board duplication workflow covers those specifics.
What Makes Certain Boards Harder to Duplicate?
Not every board is a straightforward four-layer FR-4. Complexity drivers include:
- High layer count. Each additional layer pair adds imaging, alignment, and de-lamination time. A 24-layer board typically costs 3–4× more than a 4-layer equivalent.
- HDI microvias. Stacked or staggered microvias below 100 µm require X-ray CT to map reliably; laser-drilled structures can be invisible under optical scan alone.
- Flex and rigid-flex. Polyimide substrates delaminate differently from FR-4, and bend zones must be documented for mechanical fit.
- Embedded components. Resistors or capacitors buried in the laminate are not visible on surface inspection and must be detected through impedance measurement or cross-section.
- Populated-only samples. When only one board exists and it cannot be destroyed, we rely on X-ray imaging and non-contact probing, which reduces trace-width accuracy by roughly 0.3–0.5 mil compared to destructive methods.
PCB Duplication vs. PCB Replication: Is There a Difference?
In practice, the terms overlap. “Duplication” usually emphasizes the file-extraction phase — producing Gerbers and BOMs from a sample. “Replication” often implies the full cycle through to fabricated and assembled boards. At our facility both paths start the same way: a physical board goes in, verified manufacturing data comes out. The difference is whether you stop at files or continue through prototyping and volume production with us.
Pricing Signals
We quote per-project because board complexity varies enormously, but these ranges give a planning baseline:
- Simple 2-layer board (≤200 components): USD 300–600 for the file package.
- 4–6 layer board (200–800 components): USD 800–2,000.
- 8–16 layer board with controlled impedance: USD 2,500–6,000.
- 18+ layer HDI or RF board: Quoted on inspection; typically USD 5,000+.
Verification prototype fabrication is billed separately. Rush service (50 % turnaround reduction) carries a 30–40 % surcharge.
Industries That Rely on Board Duplication
PCB duplication serves any sector where hardware outlives its original documentation. We see the highest volume from industrial automation, medical devices, defense sustainment programs, and power electronics such as inverter controllers. In each case the driver is the same: the product must keep running, and the files no longer exist.
How many sample boards do you need for PCB duplication?
Ideally two: one for destructive de-lamination and imaging, one as a reference for continuity testing and verification. If only one board is available, we use non-destructive X-ray and probing methods, though trace accuracy may decrease by 0.3–0.5 mil on inner layers.
Can you duplicate a board if some components are obsolete?
Yes. Our BOM output flags every end-of-life or hard-to-source part and suggests drop-in replacements with matching footprint, electrical specs, and package. We verify substitution compatibility at the schematic level before finalizing the file set.
Is PCB duplication legal?
Duplicating a board you own — for repair, continued production of your own product, or second-sourcing — is standard engineering practice. We require proof of ownership or authorization before starting work and operate under NDA. If the board contains protected firmware, IC readout is handled only with documented authorization.
What file format should I request for my fab house?
Gerber RS-274X is universally accepted. If your fabricator prefers ODB++ or Gerber X2, we deliver in those formats at no extra charge. We also supply native Altium or KiCad project files on request for clients who plan further design modifications.
How do you handle impedance-controlled traces during duplication?
We measure the original stackup cross-section, identify controlled-impedance nets from trace geometry and routing patterns, then re-simulate using the measured dielectric constant and copper weight. The output Gerber set includes an impedance table and stackup drawing so your fab house can match the target impedance within ±5–10 % depending on layer count.
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