PCB Redraw Service | Free Feasibility Check in 24 Hours

What Is a PCB Redraw Service?

A PCB redraw service takes a physical printed circuit board — often the only surviving reference — and produces a complete, manufacturable set of design files: Gerber/ODB++, bill of materials, and optionally a full schematic. Our engineers photograph, scan, and measure the original board layer by layer, then redraw every trace, via, pad, and plane in CAD to deliver files that a fabrication house can run without modification. The result is a digital twin of a board that may have been designed decades ago, with no design data ever archived.

When Do You Actually Need a PCB Redraw?

Not every situation calls for a full redraw. Here are the scenarios where it makes the most practical sense:

• Original design files lost. The engineer retired, the company was acquired, or the hard drive failed. No Gerber, no schematic, no BOM — just a working board.
• Legacy equipment still in production. The board runs a test instrument or industrial controller that must stay in service, but the OEM no longer supports it.
• Second-source qualification. You need to move fabrication to a new vendor and require verified Gerber data rather than trusting an old photoplot.
• Cost-reduction redesign baseline. Before optimizing a board for cheaper materials or fewer layers, you need an accurate starting-point schematic and layout. A redraw gives you that baseline for a PCB cost reduction redesign.
• Failure analysis and repair support. A redrawn schematic lets field engineers trace faults without guessing net connectivity from visual inspection alone.

How Our PCB Redraw Process Works

Step 1 — Feasibility Assessment (Free, 24 Hours)

Ship us one board (or high-resolution photos of both sides). Within one business day our team evaluates layer count, minimum feature size, BGA presence, and any obvious damage. You receive a written feasibility report with a firm quote and timeline — no charge, no obligation.

Step 2 — High-Resolution Imaging and Layer Separation

We capture the board at 2400+ DPI optical resolution. For multilayer designs (4 layers and above), we use controlled chemical or mechanical layer separation to expose each copper layer individually. On high-density boards with buried vias, we supplement with X-ray imaging to map internal via stacks without destroying the sample.

Step 3 — CAD Redraw

Each layer image is imported into Altium Designer or equivalent EDA software. Engineers manually trace every feature, cross-referencing physical measurements taken with calibrated tools. Pad geometries are matched to IPC-7351 land patterns; trace widths and spacing are verified against the original copper. Net connectivity is confirmed with continuity testing on the physical board.

Step 4 — BOM Extraction

Every component is cataloged: part markings, package type, orientation, and reference designator. Where markings are worn, we use parametric measurement and datasheet matching to identify the correct part number. BOM accuracy typically exceeds 98% on boards with legible markings.

Step 5 — Schematic Capture (Optional)

If you need a schematic — not just Gerber — our engineers back-annotate the layout into a hierarchical schematic with meaningful net names and functional block grouping. This is a separate deliverable often requested for maintenance documentation. Learn more about our schematic capture service and its typical lead times.

Step 6 — Verification and Delivery

Final Gerber files run through DRC and are cross-checked against the original board dimensions, mounting holes, and connector placements. We deliver a complete package: Gerber RS-274X or ODB++, drill files, BOM (Excel + CSV), centroid/pick-and-place data, and schematic PDF if ordered.

What Can — and Cannot — Be Redrawn

Accuracy and Tolerances

Accuracy is the single most important metric in a PCB redraw service. Loose tolerances mean the redrawn board won’t fit the enclosure, impedance will shift, or BGAs won’t solder properly. Here is what our process delivers:

• Trace/space accuracy: 3 mil (0.076 mm) on standard FR-4; 3.5 mil on boards with heavy oxidation or solder mask bleed.
• Drill registration: ±2 mil (0.05 mm) hole-to-pad alignment, verified against the physical board.
• Board outline: ±5 mil (0.127 mm) on overall dimensions, including cutouts and slots.
• Impedance-controlled traces: Stackup is reconstructed from cross-section measurements; dielectric thickness is measured to ±0.5 mil. Impedance targets are documented but require fab-house confirmation during production.

These numbers reflect real-world results on production boards. Corroded or heavily reworked areas will have wider tolerances, and we flag every such zone in the deliverable notes.

Deliverable Formats

Pricing Signals

Exact pricing depends on layer count, board area, component density, and whether schematic capture is included. As a rough guide:

• Simple 1–2 layer boards (under 100 × 100 mm, ≤50 components): starting around $300–$600.
• 4–6 layer boards with moderate BGA density: typically $800–$2,000.
• 8+ layer or HDI boards: quoted individually after feasibility review; most fall in the $2,000–$6,000 range depending on complexity.
• Schematic capture add-on: adds roughly 30–50% to the base redraw cost.

Volume discounts apply when you need multiple boards redrawn in the same project. If your goal is to move straight into production after the redraw, ask about our fast PCB copy service that bundles redraw with fabrication and assembly.

What Sets a Good PCB Redraw Apart from a Bad One

Many vendors claim to offer PCB redraw, but the gap between a usable deliverable and a problematic one is enormous. Here are the failure modes we see when clients come to us after a poor first attempt elsewhere:

• Auto-traced Gerber with no manual cleanup. Software auto-trace introduces artifacts — merged pads, broken traces at acute angles, phantom copper. Every auto-traced file must be manually verified net-by-net.
• Missing or incorrect BOM. Worn markings get guessed instead of measured. A 10 kΩ resistor logged as 10 Ω will cause board failure.
• No DRC run. Files that pass a basic visual check may still violate minimum annular ring, clearance, or solder mask rules at the fab house.
• Ignoring stackup. On multilayer boards, simply capturing copper patterns without reconstructing the stackup means impedance-sensitive nets (USB, LVDS, DDR) will not perform correctly in the clone.

Our process addresses each of these by combining high-resolution imaging, physical measurement, manual CAD work, and DRC verification before any file leaves our lab.

Frequently Asked Questions

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