PCB Reverse Engineering Deliverables: What You Get

You send a physical board to a reverse engineering lab. Weeks later, a file package arrives. But what is actually inside that package, and how do you judge whether the work is complete? Understanding PCB reverse engineering deliverables before a project starts prevents scope disputes, saves review cycles, and ensures the recovered data is genuinely manufacturable—not just a collection of pretty pictures.

This article walks through every file type you should expect, explains the purpose each one serves, and provides practical quality checks you can run the moment the deliverables land on your desk. If you are still evaluating whether you need a board-level reverse engineering engagement, start there first; this page assumes you have already committed and want to know what “done” looks like.

Overview of a Complete Deliverable Package

A professional lab typically delivers between five and eight distinct file sets. The exact count depends on the project scope—some clients only need a schematic, others need a full manufacturing data package ready to send to a contract manufacturer. The table below summarizes the standard deliverables, their formats, and the downstream use case each one addresses.

Not every project produces every row. A client who only needs to extract a hierarchical schematic from a finished board will receive the schematic, BOM, and netlist—but may not need Gerber files at all. Clarify scope up front.

Gerber and Layout Files: The Fabrication Backbone

Gerber files are the lingua franca of PCB manufacturing. Each copper layer, solder-mask layer, silkscreen layer, and paste layer gets its own Gerber file. Drill data arrives as an Excellon file. Together, these files let any qualified fabrication house produce a bare board without asking a single question.

What to Check When You Receive Gerbers

• Layer count match. Open the files in a free viewer (GerberView, KiCad’s Gerber viewer, or Ucamco’s Reference Gerber Viewer) and confirm the number of copper layers matches the original board.
• Board outline. The mechanical layer or board-edge Gerber should define the exact profile, including cutouts and slots.
• Drill file alignment. Load the drill file on top of the copper layers. Every pad that needs a hole should have one, and no drill hits should land in the middle of a trace.
• Minimum trace/space. Ask the lab for the minimum feature sizes they recovered. If the original board had 3-mil traces, confirm those are preserved—not rounded up to 5 mil for convenience.
• Panelization data. If the original board was part of a panel, some labs include panel Gerbers; others deliver only the single-unit data. Confirm which you need.

The lab should also supply the native EDA layout file (for example, an Altium .PcbDoc) so you can make modifications later. A Gerber-only delivery locks you into a snapshot; an editable layout gives you a living design. This distinction matters if you plan to move from recovered files to a first-article prototype.

Schematic: The Intellectual Core of the Project

The schematic is often the most labor-intensive deliverable. It is not simply a netlist drawn as a picture; a good recovered schematic restores design intent—grouping circuits into functional blocks, labeling power rails, and arranging sheets hierarchically so a new engineer can read the design cold.

Quality Benchmarks for a Recovered Schematic

• Hierarchical structure. Power supply, digital core, analog front-end, and I/O sections should live on separate sheets, not crammed onto one page.
• Meaningful net names. Nets should be named VCC_3V3, SPI_CLK, or AUDIO_OUT_L—not Net0047.
• Reference designator consistency. Every component on the schematic must match the BOM and the silkscreen on the layout.
• Annotation completeness. Decoupling caps should be placed near the IC they serve. Connector pin-outs should be labeled. Test points should be marked.
• ERC clean. The schematic should pass an Electrical Rules Check in the native EDA tool with zero errors and only justified warnings.

If you want a deeper look at how engineers trace nets and rebuild symbols, the guide on reverse engineering a PCB to schematic covers the methodology step by step.

Bill of Materials (BOM): Every Part, Every Value, Every Source

The BOM is a spreadsheet that lists every component on the board. A professional BOM goes well beyond reference designator and value; it includes manufacturer part numbers (MPN), package footprints, distributor stock links, and—critically—notes on any parts that required special identification effort.

Columns You Should Expect

Pay special attention to the Notes column. Some components arrive with sanded markings, house numbers, or obsolete date codes. The lab should flag these explicitly and, where possible, suggest form-fit-function substitutes. If several parts on your board are end-of-life, ask the lab about their approach to sourcing replacements—supply-chain continuity is often as important as the electrical data itself.

Netlist: The Electrical Truth Table

A netlist is a machine-readable list of every electrical connection on the board. It is the bridge between schematic and layout: if the netlist is correct, the board will function; if it contains even one wrong connection, you have a dead prototype.

How the Netlist Is Verified

1. Schematic-to-layout cross-check. The EDA tool generates a netlist from the schematic and compares it against the layout netlist. Any mismatch triggers an error.
2. Physical continuity test. A flying-probe or bed-of-nails tester checks the recovered Gerber data against the netlist. This catches opens and shorts that might hide in inner layers.
3. IPC-D-356 export. Many labs deliver the netlist in IPC-D-356 format, which bare-board test houses can import directly into their fixtures.

The netlist is also the file your contract manufacturer uses for in-circuit test (ICT) fixture development. Without it, the CM has to reverse-engineer the test points themselves—adding cost and time.

Fabrication Notes and Stack-Up Documentation

Gerber files tell a fab house what to etch; fabrication notes tell them how to build the sandwich. A complete fab-note package includes:

• Layer stack-up diagram showing copper weights, dielectric materials (FR-4, Rogers, polyimide), and thicknesses.
• Impedance control requirements for differential pairs and single-ended controlled-impedance traces, including target impedance, tolerance, and reference layers.
• Surface finish specification (HASL, ENIG, OSP, immersion silver).
• Solder-mask and silkscreen color.
• Drill table listing finished hole sizes, plating requirements, and tolerances.
• Special instructions such as back-drill depth, via-in-pad with cap-and-fill, or edge plating.

For multi-layer boards—especially those with blind or buried vias—the stack-up documentation is derived from cross-sectioning or micro-CT scanning during the reverse engineering process. If the original board used unusual materials (high-Tg laminates, ceramic substrates), the fab notes should call this out so your fabricator can quote accurately.

Assembly Drawings and Pick-and-Place Data

Assembly drawings show component placement, polarity markings, and keep-out zones. They are used by SMT operators, rework technicians, and quality inspectors. A good assembly drawing includes:

• Top and bottom views with reference designators.
• Polarity indicators for diodes, electrolytic caps, and ICs (pin-1 dots).
• Notes on any hand-soldered or glued components.
• Board-level conformal-coating zones, if applicable.

The pick-and-place file is a CSV containing the X-Y coordinates and rotation angle of every SMD component. Your contract manufacturer feeds this directly into the placement machine. If the coordinates are off by even 0.1 mm on a fine-pitch QFP, you get solder bridges.

Native EDA Project Files: Future-Proofing Your Investment

The most valuable deliverable is often the one clients forget to request: the complete, editable EDA project. This includes the schematic sheets, the board layout, the component library (footprints and symbols), and the design rules. With these files, you can:

• Run a DRC (Design Rule Check) and verify manufacturability against your chosen fab house’s capabilities.
• Issue ECOs (Engineering Change Orders) without starting from scratch.
• Swap components, adjust trace widths, or add test points for a new product variant.
• Generate fresh Gerbers any time you change fabricators.

If you are weighing whether you need editable design files or just a one-to-one board copy, the comparison between a faithful copy and an editable reverse-engineered design clarifies the trade-offs.

How to Review Deliverables: A Practical Checklist

When the file package arrives, work through this checklist before signing off:

1. Open every file. Confirm nothing is corrupt, zero-byte, or in a format you did not agree on.
2. Layer count audit. Count copper layers in the Gerber set and compare to the stack-up document.
3. Schematic-to-layout netlist comparison. Run the EDA tool’s built-in comparator. Zero mismatches is the only acceptable result.
4. BOM spot check. Pick ten random components and verify the MPN matches the package footprint on the layout and the symbol on the schematic.
5. Impedance note review. If the board has high-speed signals, confirm the fab notes specify impedance targets and the layout shows the correct trace widths on the correct reference layers.
6. Drill file sanity check. Overlay the drill file on the layout. Look for missing vias, especially in BGA fan-out areas.
7. Assembly drawing vs. BOM. Every reference designator on the assembly drawing should appear in the BOM, and vice versa.
8. Pick-and-place coordinate check. Import the CSV into the EDA tool or a viewer and confirm component centroids align with pads.

If you have questions about any step, the reverse engineering FAQ answers the most common buyer concerns.

What Happens After Delivery

Receiving files is not the finish line—it is the starting gate for manufacturing. Most clients follow one of two paths:

• Direct fabrication. Send the Gerbers, drill files, fab notes, BOM, and pick-and-place file to a CM for quoting and production.
• Redesign cycle. Open the native EDA project, make modifications (swap an obsolete MCU, add an EMI filter, change the connector), regenerate outputs, and then fabricate.

Either path depends on the deliverables being complete and internally consistent. A missing fab note can add a week to a quote cycle; a wrong MPN in the BOM can delay procurement by months if the part is long-lead.

Protecting the Deliverables

Recovered design data is sensitive intellectual property. Before the project begins, ensure the lab has signed an NDA that covers data handling, storage duration, and sample return. A clear understanding of NDA terms and data-handling protocols protects both parties and gives you legal recourse if files are mishandled.

On your side, store the deliverables in a version-controlled repository with access logging. Treat them exactly as you would original design files—because, functionally, that is what they are.

Summary

A complete set of PCB reverse engineering deliverables transforms an unknown physical board into a fully documented, editable, manufacturable design. The core package—Gerber files, schematic, BOM, netlist, and fabrication notes—covers fabrication and assembly. The native EDA project extends the value into future redesign cycles. And thorough verification at delivery time ensures you never discover a gap at the worst possible moment: on the production floor.

If you are ready to start a project or want to understand the full workflow from scanning to final verification, explore the full range of reverse engineering services available.

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