Our Complete PCB Copy Portfolio
This PCB copy portfolio represents over 200 board-recovery projects completed across industrial controls, medical devices, telecommunications, automotive electronics, and consumer products. Every entry below reflects a real engagement—anonymized to protect client IP—where our engineers extracted manufacturable Gerber files, BOMs, and schematics from physical boards with no surviving documentation. Browse by layer count, board class, or industry to gauge whether your project falls within our proven capabilities.
What Does a PCB Copy Portfolio Actually Show?
A credible PCB copy portfolio is not a gallery of stock photos. It is a structured record of board complexity, recovery method, deliverable format, and verification outcome. Each project entry in our portfolio includes the board’s layer count, minimum trace/space, component count, whether firmware recovery was involved, and the final deliverable set (Gerber RS-274X, ODB++, BOM in Excel, schematic in PDF or Altium/KiCad format). This transparency lets you compare your board against projects we have already completed and make an informed decision before shipping anything.
Portfolio Breakdown by Layer Count
| Layer Count | Projects Completed | Min Trace/Space Achieved | Typical Turnaround | Common Industries |
|---|---|---|---|---|
| 1–2 layers | 80+ | 6/6 mil (0.15/0.15 mm) | 3–5 working days | Consumer, LED drivers, power supplies |
| 4 layers | 60+ | 4/4 mil (0.10/0.10 mm) | 5–8 working days | Industrial control, IoT gateways |
| 6 layers | 30+ | 3.5/3.5 mil (0.09/0.09 mm) | 8–12 working days | Telecom, motor drives |
| 8–10 layers | 20+ | 3/3 mil (0.076/0.076 mm) | 10–15 working days | Medical, automotive ECUs |
| 12–16 layers | 12+ | 3/3 mil (0.076/0.076 mm) | 15–20 working days | Aerospace, server/networking |
Four-layer boards remain our most requested category. If you are wondering whether inner-layer extraction is realistic, our guide on copying a 4-layer board step by step walks through the delayering and imaging process in detail.
Portfolio Categories by Industry
Industrial Automation & Control
PLCs, VFD control boards, HMI interface cards, and proprietary sensor-conditioning modules from equipment lines discontinued 10–25 years ago. Typical boards: 4–6 layers, FR-4 Tg 150–170 °C, through-hole + SMD mix, 100–400 components. Many include microcontrollers (PIC, STM32, Renesas) requiring firmware readout under authorized recovery. One representative project involved a 6-layer Siemens-era motor-drive board with 287 components; we delivered verified Gerbers, a 100 % cross-referenced BOM, and a schematic within 11 working days.
Medical & Laboratory Equipment
Boards from patient monitors, centrifuge controllers, and diagnostic instruments where the OEM no longer supplies spares. IPC Class 2/3 standards apply. We document controlled-impedance traces (typically 50 Ω single-ended, 90–100 Ω differential) and flag any safety-critical net separations. Layer counts range from 4 to 10; component counts from 150 to 600+.
Telecommunications & Networking
Line cards, base-station amplifier modules, and legacy PBX boards. High-speed design constraints dominate: impedance-controlled differential pairs, blind/buried vias, and BGA packages down to 0.5 mm pitch. Our portfolio includes 8- and 12-layer telecom boards where we successfully reconstructed full via stacks and verified signal-integrity constraints before fabrication.
Automotive & Transportation
ECU boards, body-control modules, and aftermarket tuning controllers. Conformal coating removal and potting compound extraction are routine prerequisites. Boards often use aluminum-core or ceramic substrates for thermal management, and firmware is frequently locked behind OTP or RDP protection.
Consumer Electronics & IoT
Smart-home hubs, wearable sensor boards, and legacy audio equipment. Typically 2–4 layers, high component density, compact form factors. Fast turnaround—often 3–5 working days for single- and double-sided boards.
For a deeper look at how recovery helps keep discontinued equipment running, see our page on reverse engineering for repair and downtime reduction.
Representative Project Snapshots
Snapshot 1 — Legacy PLC I/O Card (4 Layers)
- Board: 4-layer, 160 × 100 mm, FR-4, 1.6 mm thickness
- Components: 212 (mix of SOIC, QFP-64, through-hole connectors)
- Challenge: No documentation; OEM ceased production in 2006
- Method: Optical scanning at 2400 DPI per layer, chemical delayering of inner layers, manual net verification against physical continuity
- Deliverables: Gerber RS-274X (all layers + drill), BOM with 3 cross-referenced suppliers per line, schematic (PDF + Altium .SchDoc)
- Turnaround: 7 working days
- Outcome: Client fabricated 50 replacement boards; first-pass yield 98 %
Snapshot 2 — Medical Centrifuge Controller (8 Layers)
- Board: 8-layer HDI, 95 × 72 mm, impedance-controlled, via-in-pad
- Components: 384 (BGA-256 MCU, 0201 passives, shielded inductors)
- Challenge: Controlled-impedance differential pairs for USB 2.0 and SPI bus; MCU firmware locked (STM32F4, RDP Level 1)
- Method: Cross-section analysis for stackup confirmation, 4000 DPI imaging, impedance simulation in Si9000, authorized firmware recovery
- Deliverables: Gerber + ODB++, impedance report, BOM, schematic, recovered .bin firmware
- Turnaround: 14 working days
- Outcome: Client validated 5 prototype boards; all passed functional test
Snapshot 3 — Telecom Line Card (12 Layers)
- Board: 12-layer, 233 × 160 mm, blind + buried vias, ENIG finish
- Components: 510+ (BGA-484 FPGA, DDR3 memory, high-speed connectors)
- Challenge: Reconstructing blind via stacks without destroying the only sample board
- Method: Non-destructive X-ray tomography for via mapping, followed by selective micro-section of scrap edge; high-resolution layer imaging
- Deliverables: Full Gerber set, stackup drawing with dielectric constants, BOM, partial schematic (FPGA I/O mapping)
- Turnaround: 19 working days
- Outcome: Fabrication at IPC Class 2; 6 boards delivered, 5 passed all signal-integrity checks
More detailed project narratives, including a real-world case study of six diverse boards we recovered, are available for engineers who want to compare complexity levels.
Standard Deliverables Across All Portfolio Projects
| Deliverable | Format | Included By Default |
|---|---|---|
| Gerber files (all layers + drill) | RS-274X / Gerber X2 | Yes |
| Pick-and-place data | CSV | Yes |
| Bill of Materials | Excel (.xlsx) | Yes |
| Schematic | PDF + native EDA (Altium / KiCad) | Yes (4+ layer boards) |
| Stackup drawing | Yes (4+ layer boards) | |
| Impedance report | PDF (Si9000 output) | On request / controlled-impedance boards |
| Firmware binary | .bin / .hex | When authorized & feasible |
| ODB++ package | .tgz | On request |
Every file set ships after DRC and ERC verification. Our quality guarantee policy details the re-work commitments we make if any deliverable does not match the source board within stated tolerances.
How We Verify Before a Project Enters the Portfolio
A board only earns a place in our PCB copy portfolio after it passes three gates:
- Design Rule Check (DRC): automated Gerber verification against the fab’s manufacturing constraints—annular ring, solder mask clearance, minimum drill.
- Electrical Rule Check (ERC): netlist comparison between the extracted schematic and the physical board’s continuity, tested at ≥ 20 random nets per 100 components.
- Prototype Validation: for complex boards (≥ 6 layers or controlled impedance), we recommend a 3–5 piece prototype run. If the client authorizes it, we oversee fab and report first-pass yield.
Understanding our full scan-to-build pipeline helps set expectations. Our step-by-step PCB copy process page covers each stage from intake to final file delivery.
What We Decline
Transparency matters. We do not accept projects where the submitter cannot demonstrate ownership or authorization for the board being copied. We also decline boards with active patent-infringement risk that the client cannot address. Our legitimate use policy explains the documentation we require and the types of jobs we turn away.
How many boards are in your PCB copy portfolio?
Our portfolio includes over 200 completed recovery projects spanning 1-layer through 16-layer boards. The count grows monthly. Each project is anonymized but retains full technical detail—layer count, component count, trace/space, turnaround, and deliverable list—so prospective clients can find a close match to their own board.
Can I see a sample deliverable before committing?
Yes. We offer a sample evaluation on select project types. You ship one board, we image the outer layers and provide a partial Gerber preview plus a feasibility report at no obligation. This lets you judge extraction quality before authorizing the full project.
Do you recover firmware as part of every portfolio project?
Not automatically. Firmware recovery is performed only when the client owns the IP or provides written authorization, and only when the target MCU’s protection level makes extraction technically feasible. Locked chips at the highest protection tiers (e.g., STM32 RDP Level 2) are not recoverable. We assess feasibility during intake and quote firmware recovery as a separate line item.
What if my board is more complex than anything in your portfolio?
We evaluate every submission individually. If your board exceeds 16 layers, uses exotic substrates (Rogers, ceramic), or has unusual constraints, we run a feasibility assessment first. About 5–8 % of submissions fall outside our current capabilities, and we will tell you upfront rather than accept a project we cannot deliver.
How do I submit a board for evaluation?
Ship the physical board to our lab or upload existing files (photos, partial schematics, X-rays) through our secure transfer portal. We respond with a feasibility assessment and quote within 1–2 working days.
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