When you request a sample evaluation, an engineer looks at your actual board or chip — photos first, physical sample if needed — and tells you three things: whether the job is feasible, what the deliverables would be, and what it costs and takes. No charge for the assessment, and no obligation. Most evaluations come back within a business day or two once we have usable photos.
This page tells you what to send, how we read it, and where we say no.
What we need from you to start a sample evaluation
Bad photos are the single biggest cause of a slow or vague quote. A phone camera is fine — the lighting and framing matter far more than the megapixels.
- Top and bottom photos, whole board in frame. Lay the board on a dark, non-reflective surface. Shoot straight down, not at an angle. Fill the frame with the board.
- Diffuse light, no flash. Flash blows out solder mask and hides silkscreen. Window light or a desk lamp bounced off a wall works better.
- Close-ups of every marked IC. Angle the light across the package so laser-etched markings catch a shadow. If a marking is sanded off or the part is under potting, say so.
- Board dimensions in mm or inches, plus board thickness if you can measure it with calipers.
- Layer count if you know it. If you don’t, we’ll estimate from via structure and edge inspection.
- One line on what you actually need. “Gerbers so I can rebuild 50 units,” “a schematic for repair,” “the firmware out of this STM32 because the developer is gone.” That single line changes the quote more than anything else.
- Quantity and timeline if you’re heading toward production.
For an IC unlock or firmware job
Send the full chip marking line by line, including the date code and revision suffix. An STM32F103C8T6 and an STM32F103CBT6 are not the same evaluation. Tell us how many chips you have, whether any are spare or sacrificial, whether the part is still populated on a board, and whether the design is potted or conformally coated. If you know the programmer already reports the device as protected or blank, mention it — that’s useful information, not a problem.
When we ask for the physical board
Photos are enough to quote most jobs. We ask for the sample itself when the work needs inner-layer access, when the silkscreen is illegible, when a BGA hides nets under the package, or when you want a working prototype built and tested. Two identical samples help — one can be sacrificed for layer separation while the other stays intact as the golden reference.
What our engineers actually look at
An evaluation is not someone glancing at a photo and typing a number. Here’s the sequence.
- Board class and construction. Layer count, board size, minimum trace and space, via type. Blind and buried vias, or any HDI stack with microvias, moves the job into a different bracket immediately because the layers can’t be recovered by simple sanding — they have to be imaged in sequence.
- Component census. How many unique part numbers, how many total placements, how many parts have illegible or scrubbed markings. Passives get measured; actives get cross-checked against the marking database and the footprint. Anything ambiguous is flagged, not guessed.
- The hard parts. Fine-pitch BGAs, QFNs with thermal pads, magnetics with unknown turns ratios, potted modules, custom or house-marked ICs. These are what determine whether the job is a few days or considerably longer.
- Special electrical requirements. Controlled impedance, RF sections with tuned stubs and grounded coplanar waveguide, high-current planes. On an RF board the copy has to preserve dielectric constant and stack-up, not just the copper geometry, so the material choice becomes part of the quote.
- Programmable devices. Which MCU, CPLD or serial flash is on the board, and whether any of them need code recovered for the copy to be functional. A board copy with untouched firmware is a very different price from one that includes firmware extraction.
- Deliverable mapping. Finally we match all of that to what you asked for. Gerbers only, Gerbers plus BOM, full schematic capture, editable CAD, or a built and tested prototype.
For boards with dense inner routing we may recommend non-destructive scanning of the board before any layer separation so there’s a verified reference to check the recovered artwork against later.
What comes back to you
A written evaluation, not a sales email. It contains:
| Item | What you get |
|---|---|
| Feasibility | Yes, yes with conditions, or no — with the reason stated plainly |
| Scope | Layer count we identified, unique part count, flagged components, sections needing special handling |
| Deliverables | Exact file list: Gerber set, drill file, netlist, BOM, pick-and-place, schematic, editable CAD, or prototype units |
| Lead time | A working-day range per stage, not a single optimistic number |
| Price | Firm for a defined scope; a range where an unknown is genuinely unresolved until we have the board |
| Open questions | What we still need from you, and how each answer moves the price |
If you asked for a prototype, the response also covers whether we’d build it as a bare board or a populated assembly, and whether component sourcing is on us or on you. That path is described in more detail on our page about building a working prototype from a physical sample.
What drives the price and the schedule
We don’t publish a number because two boards of the same size can differ by an order of magnitude in effort. The levers are:
- Layer count. Two layers can be imaged from both faces. Four, six, eight and up require the inner layers to be separated and imaged one at a time, then re-registered against each other and against the drill map.
- Board area and density. A dense 100 mm × 80 mm controller with 600 placements takes longer than a sparse 300 mm × 200 mm backplane.
- BGA presence and pitch. A 0.5 mm pitch BGA hides nets that nothing on the surface reveals. X-ray plus careful layer work is the only honest way through it.
- Unique component count. Identification effort tracks unique part numbers, not total placements.
- Obsolete or unmarked parts. Finding a form-fit-function replacement for a discontinued controller is engineering work, and it’s the part customers most often forget to budget for.
- Deliverable depth. Gerbers are the floor. A verified schematic with net names and functional blocks costs more because the engineer has to understand the circuit, not just trace it.
- Firmware. Whether any code needs to come off a protected part, and which family it is.
Acceptability of anything we fabricate is judged against IPC-A-600 for visual criteria and IPC-6012 for performance class, and we’ll ask which class you need — a Class 2 industrial board and a Class 3 board destined for medical or avionics use carry different inspection cost. Trace width choices in a redrawn layout follow IPC-2152 for current-carrying capacity rather than being copied blindly when the original was marginal.
Cases that are harder, and cases we decline
This is where most competitors go quiet. Being straight about limits saves both of us a week.
Harder, but usually doable
- Potted or epoxy-encapsulated assemblies. Recoverable, but the removal is slow and some parts don’t survive it. Two samples strongly preferred.
- Flex and rigid-flex. Thin dielectrics and adhesive layers make separation delicate, and the bend geometry has to be documented as well as the copper.
- HDI with stacked microvias. Every level has to be resolved individually and the via chain reconstructed.
- House-marked or custom-programmed logic. A CPLD with a scrubbed part number needs pin-behavior analysis before we can even name the device.
- Boards with heavy field damage. A burned power section may have destroyed the copper we need to read. A second, non-failed unit fixes this instantly.
Where the answer may be no
- Modern MCUs at their highest protection setting. On STM32 parts, RDP Level 1 and Level 2 are not the same problem, and Level 2 permanently disables debug access. On MSP430 a blown JTAG fuse or an unknown BSL password changes the picture. On 8051 and AVR parts the specific lock-bit and security-fuse configuration decides it. We’ll tell you which category your part falls in during the evaluation rather than after you’ve paid.
- Chips with hardware secure enclaves or on-die encrypted flash. Often not feasible, and we say so.
- A single irreplaceable sample where the only viable method is destructive. We won’t take that risk without telling you the sample may not come back.
- Anything where the requester clearly doesn’t hold rights to the design. We decline those.
On that last point: you’re responsible for holding the rights to the design or for having authorization from whoever does, and for complying with the IP law that applies to you. Every project runs under NDA, and the legitimate cases we see daily are lost source code, out-of-production equipment that still has ten years of service life, obsolete parts forcing a migration, failure analysis, and authorized security work. Our lab background and how we handle customer material covers the confidentiality side.
Frequently asked questions
Is the sample evaluation really free
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote
Related reading
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote