A PCB clone service takes a physical board you already have and rebuilds the manufacturing data set — copper layers, drill file, silkscreen, BOM, and stackup — so you can order the same board again. You don’t need the original CAD files. You do need to send at least one board, and ideally two: one to work on and one to keep intact as a reference.
That’s the short answer. The rest of this page is the detail an engineer actually needs before committing a board to a courier.
What “clone” means here, and where it stops
Cloning is layout-level duplication. The output is a board that is dimensionally and electrically the same as the original: same outline, same hole pattern, same copper geometry, same part placements. It is not a redesign, and it is not automatically a schematic.
People conflate three different jobs, so it’s worth separating them:
- Clone / duplication — copper and drill data recovered so the board can be fabricated and assembled again. No circuit understanding required for the fab house.
- Schematic recovery — nets traced back into a readable circuit diagram, with reference designators and net names. This is the piece you need if you plan to modify anything.
- Redesign — a new layout on modern parts, using the original only as a functional spec.
Most maintenance jobs only need the first. If you intend to change a current-sense resistor value, swap a regulator, or shrink the board, you need the second too, and the honest version of recovering the circuit diagram from a finished board costs more than copper duplication because a human has to interpret every net, not just image it. If the vocabulary is still fuzzy, the difference between cloning and replicating a board is worth five minutes.
What to send us, and what comes back
The quoting step is fast if you send the right things the first time. Vague inquiries turn into three days of email.
Send this
- Photos of both sides, whole board in frame, on a dark non-reflective background. Straight overhead, not at an angle. Diffuse light, no flash glare on the solder mask.
- Board dimensions — length, width, and thickness. A caliper reading beats a guess.
- Layer count if you know it, or say you don’t. We’ll determine it.
- The main chip markings — a close-up of the MCU, FPGA, or any custom-marked part, with the full line of text legible.
- One line on deliverables: Gerbers only? Gerbers plus BOM? Schematic as well? Assembled samples?
You get this back
A feasibility read (is anything on this board a problem?), a lead time, and a price. If something looks risky — a sanded-off part number, potting compound, a part we can only guess at — we say so in the quote rather than after payment.
What actually happens to your board in the lab
Order matters, because each step destroys information the next step no longer needs.
Intake and documentation. High-resolution scans of both sides, assembled, before anything is touched. Every component is photographed in place with its orientation and polarity visible. This is the only record of where the electrolytics face and which end of the diode is cathode, so it gets done properly.
Component identification. Markings are logged, cross-referenced to datasheets, and where markings are house-coded or sanded, the part is measured — resistance, capacitance, forward voltage, pinout behavior — to classify it. Unresolved parts get flagged in the BOM as “measured value, unconfirmed manufacturer,” not silently invented.
Desolder and clean. Parts come off, pads get cleaned, and the bare board is scanned again. Now the outer-layer copper is visible without packages in the way.
Layer separation. For anything beyond two layers, the inner layers have to be exposed and imaged one at a time — controlled grinding down to each copper layer, scanning, then continuing. This is why a four-layer board is not “twice a two-layer board” in time or cost. It’s a sequential, one-shot process on a physical object.
Vector reconstruction. Scans become real CAD geometry — traces with actual widths, pads with actual sizes, drills with actual diameters, not a traced bitmap. Layer-to-layer registration is checked against via positions, which is the only alignment reference that exists once the silkscreen is gone.
Verification. The rebuilt data is checked back against the intact reference board: continuity on nets sampled across the board, drill count and diameters against the original, dimensions against caliper measurements, and a design rule check on the output. Where via structures are ambiguous, X-ray settles it. Board acceptability criteria from IPC-A-600 and IPC-6012 are the language we use when specifying the rebuilt board to the fab, so annular ring, plating thickness, and mask registration expectations come across in terms a fab already understands.
Which boards are harder, and which we sometimes decline
This is the part most competitors leave out. Feasibility is not uniform.
| Board type | Difficulty | Why |
|---|---|---|
| 2-layer through-hole | Straightforward | Both copper layers visible after cleaning; nets confirmable with a meter |
| 4–6 layer, SMT | Moderate | Inner layers require sequential separation; power planes are easy, signal layers need care |
| 8+ layer with BGAs | Involved | Every inner layer imaged separately; BGA nets are invisible from outside and need X-ray plus careful registration |
| HDI, blind and buried vias | Hard | Via structure must be reconstructed layer-pair by layer-pair; stackup guessing is not acceptable here |
| Controlled impedance / RF | Hard | Geometry alone isn’t enough — dielectric thickness and Dk affect whether the copy performs like the original |
| Potted or epoxy-encapsulated | Case by case | Removal risks destroying traces; sometimes the board underneath is not recoverable at all |
| Board with locked MCU firmware | Separate question | Copper duplication and code recovery are two different projects with two different feasibility answers |
Other things that genuinely change the answer: heavy corrosion or burned-through areas, missing or already-removed components, conformal coating that has bonded into the mask, and single-sample jobs where there’s no spare board to verify against. Custom ASICs and house-marked programmable logic can be identified physically but not necessarily sourced — we’ll tell you that at quote time, not at delivery.
On the layer-count question specifically, a clean two-layer board copy is the fastest, most predictable job in this shop, and it’s a reasonable place to test how a vendor works before you hand over the dense multilayer one.
What drives the price and the schedule
We won’t post a number, because a number without your board attached is fiction. Here’s what moves it:
- Layer count — the single biggest factor, because each inner layer is a separate imaging pass
- Board area and component count — 800 parts takes longer to identify and place than 60
- BGA and fine-pitch presence — hidden nets, X-ray time, harder rework on assembly
- Deliverable set — Gerbers and drill only, versus Gerbers plus BOM plus netlist plus schematic plus assembled samples
- Whether firmware is involved — a locked microcontroller is a separate feasibility assessment
- Sample condition — a working intact board is cheaper to clone than a cracked, corroded one
On timing: a simple two-layer board is usually a matter of days. A dense multilayer board with BGAs and a full BOM is meaningfully longer, and if you also want assembled and tested samples, add fabrication and assembly lead time on top of the engineering time. Anyone quoting a fixed turnaround before seeing photos is guessing.
Legitimate use, and who owns what
The work we do lands overwhelmingly in four places: keeping out-of-production industrial equipment running, replacing a board whose original vendor has disappeared, restoring design data a company owns but lost through staff turnover or a dead server, and dealing with component obsolescence when a part in a working design goes end-of-life.
You’re responsible for holding the rights to the design you send, and for complying with applicable IP law in your jurisdiction. We work under NDA, files stay with you, and we don’t build your board for anyone else. That’s the whole of it.
Frequently asked
Do you need the original schematic to clone my board?
No. The board itself is the source of truth. We recover copper geometry from the physical layers and identify parts from markings and measurement. A schematic, if you happen to have a partial one, speeds up net verification and helps resolve ambiguous parts — but it’s a bonus, not a requirement. Most boards that reach us arrive with no documentation at all.
Will the cloned board work exactly like the original?
For the large majority of digital and power boards, yes — same geometry, same parts, same behavior, and we verify samples before shipping. The honest exceptions are RF and tightly controlled-impedance designs, where laminate properties matter as much as copper, and boards containing custom silicon we can identify but not buy. We flag those before you commit.
How many boards should I send?
Two is ideal: one gets consumed by layer separation, one stays intact as the verification reference and for continuity checks. If you can only spare one, we can still work — we’re just verifying against photographs and measurements taken before disassembly instead of against a live board, which is a slightly weaker check.
Can you also copy the firmware in the microcontroller?
Sometimes, and it’s a separate project with its own feasibility answer. It depends
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote