24 Layer PCB Reverse Engineering | What Layer Count Changes

24 layer PCB reverse engineering recovers a full schematic, Gerber set, and BOM from a board with 24 copper layers — typically found in telecom backplanes, high-speed networking switches, and advanced medical imaging systems. At this layer count, the work shifts from straightforward trace-tracing to managing 23 dielectric interfaces, multiple buried and blind via stages, and tight impedance envelopes that must be reconstructed within ±5 % of the original design intent. Understanding what changes at 24 layers — and what can go wrong — is critical before committing a board to destructive analysis.

Why Is 24 Layer PCB Reverse Engineering Harder Than Lower Counts?

Every additional copper layer adds a dielectric interface, a lamination cycle, and another potential via stage. A 24-layer board can involve four to six sequential lamination presses, each embedding buried vias that are invisible from the surface. Compared to a standard 8- or 10-layer project, the jump to 24 layers multiplies delamination risk during cross-sectioning and demands far more imaging passes.

Key Complexity Drivers

The trace/space on inner layers often drops to 3/3 mil or below because designers pack differential pairs between ground planes. Missing a single via span during analysis means an entire signal path is lost, so our engineers map every via type before delamination begins.

The Sequential Lamination Problem

A 24-layer board is not simply pressed in one shot. Fabricators build sub-stacks — for example, a 6-layer core with buried vias on L10–L15, then laminate additional layers on each side in successive presses. Each press cycle bonds prepreg at 180–200 °C under 250–400 psi, permanently encapsulating the buried vias. During reverse engineering, we must reverse this sequence precisely. If we misidentify the lamination order, the via span assignments cascade errors into the netlist. On a recent telecom switch board, we identified five distinct sub-stack stages by correlating X-ray shadow density with cross-section resin flow patterns — a step that added four hours of analysis but prevented roughly 200 misrouted nets in the final Gerber output.

Our Process for 24-Layer Boards

1. Non-Destructive Inspection

We start with X-ray tomography to count layers, identify via span types (through, blind, buried, micro), and flag any embedded passives or coin-bonded thermal slugs. On a 24-layer telecom board we processed last quarter, X-ray revealed five distinct buried-via spans — information that saved roughly 15 hours of guesswork during delamination.

2. Cross-Section Micro-Photography

Multiple cross-section cuts — typically 12 to 20 per board — are photographed at 200× to 500× magnification. We measure each copper weight (commonly 0.5 oz inner, 1 oz outer), dielectric thickness (often 3.5–4.5 mil prepreg, 3.2–4.0 mil core), and confirm the lamination sequence. These measurements feed directly into the stackup reconstruction.

A worked example: on a 24-layer networking board, cross-sections revealed alternating 3.5 mil 2116 prepreg and 4.0 mil 1080 core sheets, with 2 oz copper on L1 and L24 (power distribution) and 0.5 oz on L2–L23. Total measured thickness was 3.28 mm (129 mil). This data, combined with the material Dk values, let us reconstruct impedance targets to within ±4 % of TDR-measured values on accessible outer traces.

3. Layer-by-Layer Delamination & Scanning

Chemical and thermal delamination separates each copper layer. At 24 layers, the risk of tearing thin inner-layer foils (especially ½ oz copper at 17.5 µm) is real. Our lab uses controlled-temperature baking at 180 °C followed by chemical soak to soften the resin without distorting copper. Each separated layer is scanned at 2400 DPI minimum, then vectorized into Gerber RS-274X format.

For context, 2400 DPI resolves features down to approximately 0.42 mil (10.6 µm). On boards with 3/3 mil trace/space, this gives us roughly seven pixels across the narrowest gap — enough for reliable edge detection but tight enough that scanner calibration must be verified before every session. We use NIST-traceable resolution targets to confirm accuracy.

4. Via Map & Netlist Extraction

Every via is catalogued by span (e.g., L1–L6 blind, L8–L16 buried, L1–L24 through). A 24-layer board can have 8,000–40,000 vias. We cross-reference drill files against X-ray data and physical measurements to ensure each via connects the correct layers. Netlist extraction follows, validated against schematic reconstruction.

Drill file generation for a 24-layer board often produces six to ten separate Excellon files — one per via span. Each file carries its own tool table with drill diameters ranging from 4 mil (0.10 mm) for laser-drilled microvias up to 13.8 mil (0.35 mm) for standard mechanical through-holes. Confusing spans here would create phantom connections or open nets in the final design data.

5. Impedance & Stackup Reconstruction

Controlled-impedance pairs (typically 50 Ω single-ended, 85 Ω or 100 Ω differential) must be matched to the original design. We use TDR (time-domain reflectometry) on sample traces and compare against the measured stackup geometry. Our tolerance target: ±7 % on impedance, ±0.5 mil on dielectric thickness.

Use the calculator below to estimate total board thickness based on a 24-layer configuration and adjust prepreg/core values to match your sample’s measured cross-section:

The tool above outputs nominal finished thickness. For a typical 24-layer board with standard 4.0 mil cores and 3.5 mil prepreg, expect roughly 3.0–3.4 mm (118–134 mil) total. If your physical board is significantly thinner, it likely uses thin cores (2.0 mil) or low-flow prepreg — details our engineers verify before finalizing Gerber output. If the calculator result diverges more than 10 % from your caliper measurement, the board likely contains non-standard materials such as Megtron 6 or Rogers laminates, which have different resin content and pressed thickness behavior.

What You Receive: Deliverables

• Gerber RS-274X files — all 24 copper layers, solder mask, silkscreen, paste layers, drill files (separate per via span)
• Stackup drawing — layer-by-layer with copper weights, dielectric materials (FR-4, Megtron 6, etc.), and thicknesses
• Schematic — hierarchical, in Altium or OrCAD format, with net names reconstructed from IC datasheets
• BOM — every component identified by manufacturer part number, package, and value; alternates noted where originals are obsolete
• Impedance report — measured vs. reconstructed values for each controlled pair
• ODB++ package — available on request for direct import into CAM tools

Common Applications for 24-Layer Boards

Boards at this layer count serve specific niches. Understanding the application helps our team prioritize which signals matter most during reverse engineering.

In each case, the 24-layer count exists because the designer needed dedicated ground reference planes adjacent to every signal layer, plus separate power distribution layers for multiple voltage rails (often 8–12 distinct rails on a complex switch ASIC board). Reverse engineering must capture not just the copper patterns but the intent behind the layer assignment — which layers are ground, which are power, and which carry routed signals.

What Can Go Wrong — And How We Mitigate It

Buried Via Misidentification

If a buried via spanning L10–L14 is mistakenly mapped as L10–L16, two extra layers carry phantom nets. We prevent this by correlating every via against at least two independent data sources: X-ray and physical cross-section. On boards with more than 15,000 vias, automated optical comparison catches span mismatches that manual review would miss.

Thin Dielectric Distortion

At 24 layers, some prepreg sheets are only 2.0–2.5 mil thick. During delamination, resin softening can shift copper features by up to 1 mil. Our scanning software applies fiducial-based correction using alignment marks on each layer, reducing positional error to under 0.3 mil.

Mixed-Material Stackups

High-frequency 24-layer designs sometimes combine low-loss laminates (Megtron 6, Dk ≈ 3.7) with standard FR-4 (Dk ≈ 4.2) in the same stackup. Misidentifying the material changes impedance calculations by 8–12 %. We confirm laminate type via refractive index testing and Dk measurement at 1 GHz. This step adds roughly half a day to the project but eliminates a systematic error source that would ripple through every impedance-controlled net.

BGA Escape Routing Reconstruction

24-layer boards frequently carry large BGAs (1,500–3,000+ pins) with escape routing fanning out across four to six inner layers. Pad pitches of 0.8 mm or 0.65 mm mean the dog-bone vias and traces are tightly packed. If the delamination tears even a small section of an escape layer, we reconstruct the missing geometry from the BGA pinout datasheet and the known net connectivity on adjacent layers — a manual process that can take 4–8 hours per BGA but preserves netlist integrity.

Turnaround & Pricing Signals

A 24 layer PCB reverse engineering project typically requires 20–35 working days for the complete deliverable set. Pricing starts around $4,500–$8,000 depending on board size (up to 18 × 24 in.), component density, and whether high-speed impedance verification is needed. Boards with BGA pitches below 0.65 mm or via-in-pad designs add roughly 15–20 % to both time and cost.

For boards approaching 28-layer complexity or beyond into 32-layer territory, expect additional lamination-stage analysis and proportionally longer timelines. Conversely, if your board is closer to 20 layers, the process is similar but typically 15–20 % faster.

Frequently Asked Questions

Related Services & Resources

• PCB reverse engineering services hub — overview of all board types and layer counts we support
• IoT device board reverse engineering — compact multilayer boards with wireless modules
• Heavy copper PCB recovery — power-plane-intensive boards with 3 oz+ copper

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