Blind and Buried Via PCB Reverse Engineering

Blind and buried via PCB reverse engineering recovers the complete interconnect map of high-density interconnect (HDI) boards where vias terminate inside the stackup rather than passing through every layer. Our engineers use sequential cross-sectioning, micro-CT scanning, and impedance-controlled Gerber reconstruction to reproduce these hidden structures with ±0.5 mil accuracy on via placement—delivering fabrication-ready files even when the original design data is lost.

Why Blind and Buried Vias Make Reverse Engineering Harder

A standard through-hole via is visible on both outer layers and shows up clearly on any X-ray. Blind vias connect an outer layer to one or more inner layers but stop partway through the stackup. Buried vias sit entirely between inner layers with no surface indication at all. This creates three specific problems for reverse engineering:

• Invisible connectivity: A buried via between layers 3 and 6 of a 12-layer board has zero visual presence on the surface. Standard optical scanning misses it entirely.
• Stacked and staggered microvias: HDI designs often stack laser-drilled microvias (typically 75–150 µm diameter) on top of mechanical vias, creating multi-step interconnects that require sub-layer resolution to trace.
• Non-uniform dielectrics: Sequential lamination means different prepreg thicknesses between via spans. Missing a 2-mil dielectric variation can shift impedance by 8–12%, causing signal integrity failures in the clone.

Boards with 8+ layers and ≥2 sequential lamination cycles are the most challenging. We see these routinely in networking equipment, medical imaging modules, and motherboard-class designs where BGA escape routing forces blind/buried via use.

How We Reverse Engineer Blind and Buried Via PCBs

Step 1 — Non-Destructive Imaging

We start with high-resolution 2D X-ray to identify approximate via locations and layer transitions. For boards with ≤4 mil microvias or stacked structures, we escalate to micro-CT (computed tomography) scanning at 5 µm voxel resolution. This gives us a 3D volumetric model of every via barrel, pad, and annular ring without removing a single component.

Step 2 — Component Removal and Surface Scan

All SMD and through-hole components are cataloged, photographed, and removed. We optically scan both outer layers at 2400+ DPI to capture trace geometry, solder mask openings, and via pad positions. The BOM is generated in parallel.

Step 3 — Sequential Delamination

This is the critical phase for blind and buried via recovery. We use controlled chemical etching and precision mechanical milling to expose each copper layer individually. Each exposed layer is scanned, registered to fiducial marks, and digitized into a CAD layer. For a 10-layer HDI board, this typically means 10 separate copper-layer scans plus dielectric thickness measurements between each pair.

Step 4 — Via Map Reconstruction

Our CAD engineers correlate the micro-CT data with the delaminated layer scans to build a complete via connectivity matrix. Every blind, buried, and through-hole via is assigned its start layer, end layer, drill diameter, pad size, and annular ring dimension. We flag any via-in-pad or plugged-via structures for the fabrication notes.

Step 5 — Gerber and Stackup Output

The final deliverable includes Gerber RS-274X files, an NC drill file with separate tool definitions for each via type, an IPC-2581 stackup drawing, impedance calculations, and a verified BOM. We run DRC against IPC-2223 Class 2 or Class 3 depending on the application.

What Tolerances Can You Expect?

These tolerances are sufficient for direct fabrication at most HDI-capable PCB shops. For controlled-impedance nets (common on boards requiring blind/buried vias), we include a separate impedance report with target and measured values for each differential pair and single-ended net class.

Cost and Lead Time for Blind/Buried Via Boards

Cost drivers include layer count, board dimensions, number of unique via types, and whether micro-CT is required. Boards smaller than 100 mm × 100 mm with fewer than 4 via types fall toward the lower end. Large-format multilayer boards with 16+ layers push toward the upper range. If you need files faster, our expedited reverse engineering service can compress timelines by 30–40% with a rush surcharge.

Common Failure Modes and How We Avoid Them

Blind and buried via PCB reverse engineering has specific pitfalls that less experienced labs hit repeatedly:

• Misidentified via span: A via that appears to connect layers 1–4 may actually be a stacked structure: a microvia from L1–L2 sitting on top of a buried via from L2–L4. Without micro-CT verification, the drill file will specify a single drill where two separate processes are needed. Our dual-verification (CT + delamination) catches this every time.
• Plugged via confusion: Epoxy-filled and capped vias look like pads on surface scans. We use thermal contrast imaging to distinguish filled vias from solid copper pads before assigning net connectivity.
• Impedance drift from wrong dielectric assignment: HDI stackups often use different prepreg materials (e.g., 1080 vs. 2116 glass styles) between sequential lamination stages. Assuming uniform dielectric constant across all layers introduces impedance errors of 5–15%. We measure each dielectric gap individually.
• Annular ring violations: After reconstruction, we run IPC-6012 Class 2/3 annular ring checks on every blind and buried via. Boards originally manufactured with tight tolerances sometimes have marginal annular rings that need callout in the fabrication notes to ensure the clone meets the same yield.

Which Applications Typically Use Blind and Buried Vias?

Not every board that crosses our bench has these structures. The applications that do tend to cluster in specific categories:

• Networking and telecom: Switch line cards, router modules, and 5G base station boards with high-speed SerDes routing at 25+ Gbps.
• Medical devices: Ultrasound front-end boards and patient monitoring modules where board real estate is severely constrained.
• Industrial controls: Motor controller boards and power conversion modules in compact form factors increasingly use buried vias to route high-current paths beneath signal layers.
• Consumer electronics: Smartphone and wearable main boards (typically 8–12 layer any-layer HDI).

If your board is a simpler 2-layer or 4-layer design without HDI features, the process is faster and less expensive—see our pages on recovering double-sided PCB designs for comparison.

Deliverable File Formats

• Gerber RS-274X (one file per copper layer, solder mask, silkscreen, paste)
• Excellon NC drill files — separate files for through-hole, blind, and buried drill sets
• IPC-2581 or ODB++ stackup package (layer order, materials, dielectric values)
• Impedance control report (Dk, Df, target Z₀, simulated Z₀)
• BOM in Excel/CSV with manufacturer part numbers, package types, and reference designators
• Schematic (optional, quoted separately for boards with active circuitry)

Frequently Asked Questions

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