What Is a Firmware and PCB Copy Bundle?
A firmware and PCB copy bundle is a single-project service that extracts both the physical board data (Gerber files, BOM, schematic, netlist) and the embedded firmware from every programmable IC on the board. Instead of managing two vendors or two timelines, you ship one sample and receive a complete replication package—layout files plus working binary images—ready for manufacturing or legacy maintenance.
This bundled approach eliminates the mismatch risk that occurs when hardware files arrive from one source and code from another. Our engineers verify that the extracted firmware boots correctly on a cloned prototype before final delivery, closing the gap between “files on a screen” and “board that actually runs.”
Why Bundle Firmware Extraction With Board Copy?

Ordering firmware readout separately from a board-level copy project creates three problems that a bundle solves outright:
- Timing mismatch. Gerber files may be ready in 5 days, but firmware extraction can take 10–15 days depending on chip protection. Running them in parallel inside one project compresses total lead time by 30–40%.
- Cross-reference gaps. Firmware often configures peripheral addresses, clock trees, and GPIO mappings that must match the physical layout. When one team handles both, discrepancies surface during internal review—not after you’ve ordered 500 boards.
- Cost overhead. Separate NDA contracts, separate shipping, separate project management. A bundled engagement typically saves 15–25% versus two standalone quotes for comparable scope.
What Does the Bundle Actually Deliver?
| Deliverable | Format | Notes |
|---|---|---|
| Gerber fabrication set | RS-274X / Gerber X2 | All copper, mask, silk, drill layers |
| Bill of Materials | Excel / CSV | MPN, value, package, reference designator |
| Schematic | PDF + editable (Altium / KiCad) | Hierarchical sheets for designs > 200 nets |
| Netlist | IPC-D-356A | Used for bare-board electrical test |
| Pick-and-place file | CSV with X/Y/rotation | Machine-ready for SMT lines |
| Firmware binary | .bin / .hex / .s19 | Per MCU; includes bootloader region if accessible |
| Firmware map (optional) | Flash address ranges, fuse/option-byte settings | |
| Validation report | Boot test results on cloned prototype |
For boards carrying multiple programmable ICs—say, a main ARM Cortex-M4 plus a Bluetooth SoC plus an EEPROM storing calibration data—each device gets its own binary and extraction report. A typical industrial control board with two MCUs and one serial flash adds roughly 2–4 working days versus a single-MCU design.
How the Firmware and PCB Copy Bundle Process Works
Step 1 — Sample Intake and Feasibility Scan
You ship one working sample (two if the board is expendable for cross-section). Within 24–48 hours our engineers photograph both sides under magnification, catalog every IC, and run a preliminary protection-level assessment on each programmable part. This step determines whether firmware extraction is straightforward (unlocked flash, standard JTAG/SWD) or requires advanced techniques (glitching, UV, decap).
Step 2 — Parallel Extraction
Board reverse engineering and firmware readout run simultaneously. The layout team strips solder mask, images each layer optically and via X-ray for internal planes, and reconstructs the Gerber and fabrication data from the physical board. Meanwhile, the IC team connects to each MCU’s debug port—or, if read-protection is enabled, applies the appropriate bypass under controlled conditions.
Step 3 — Cross-Verification
Extracted firmware is loaded onto a cloned prototype assembled from the recovered BOM and Gerber data. Engineers verify power-on, peripheral initialization, communication buses (UART, SPI, I²C, CAN), and basic functional behavior. If the firmware references external configuration (DIP switches, resistor-programmed addresses), those dependencies are documented.
Step 4 — Delivery and Support
You receive a single encrypted archive containing every file listed in the deliverables table above, plus a cover sheet summarizing board specs, extraction notes, and any caveats (e.g., “Bluetooth SoC firmware is OTP; binary verified but cannot be re-flashed to a blank part”). Post-delivery, we offer 30 days of Q&A support for your manufacturing team.
Typical Timelines and Pricing Signals
| Board Complexity | Layers | MCU Count | Bundle Lead Time | Starting Price Range |
|---|---|---|---|---|
| Simple consumer | 2–4 | 1 | 8–10 working days | $800–$1,500 |
| Mid-range industrial | 4–8 | 1–2 | 12–15 working days | $1,800–$3,500 |
| Complex HDI / RF | 8–16 | 2–4 | 15–22 working days | $4,000–$8,000+ |
Firmware extraction cost depends heavily on protection level. An unlocked STM32F1 read via SWD might add $200 to the project; a code-protected Renesas RH850 requiring decap and micro-probing could add $2,000+. We quote firmware line items separately inside the bundle so you see exactly where budget goes.
When a Bundle Makes Sense—and When It Doesn’t

Good candidates
- Legacy boards where the OEM no longer supports the product and you hold IP rights or a maintenance contract.
- Second-source qualification: you need a complete replication package for a contract manufacturer, including programmed ICs.
- Prototype recovery after a design-house relationship ended and source files were lost.
Poor candidates
- Boards where you only need the bare PCB layout and will write new firmware from scratch—skip the firmware line item and save cost. A standalone PCB duplication project is more appropriate.
- Products containing security-critical ICs (HSMs, secure enclaves) with no legitimate recovery path. We will flag these during feasibility and decline extraction where authorization cannot be established.
Firmware Protection Levels We Encounter
Not every MCU yields its code easily. Here is a realistic breakdown of what our lab sees across common families:
| Protection Level | Example Families | Typical Approach | Success Expectation |
|---|---|---|---|
| No protection / RDP Level 0 | ATmega, PIC16, STM32 (unlocked) | Standard debug read | >99% |
| Software read-protect (reversible) | STM32 RDP1, NXP CRP1 | Voltage glitching, debug exploit | 85–95% |
| Fuse-locked / OTP fuse | Renesas RL78, TI MSP430 | Decap + micro-probing or UV | 70–90% |
| Hardware secure element | ATECC608, TPM 2.0 | Generally not extractable | <10%; we advise against attempting |
We provide a candid feasibility assessment before you commit budget. If a part falls into the “generally not extractable” category, we say so upfront rather than billing for exploratory work with low odds.
Quality Controls Specific to Bundled Projects
Because hardware and firmware interact, our QA process includes checks that standalone services skip:
- Clock-tree audit. We verify that the firmware’s configured oscillator source (HSE, HSI, PLL multiplier) matches the crystal or oscillator on the recovered BOM.
- GPIO mapping review. Pin assignments in firmware are compared against the schematic netlist to catch any routing anomaly before prototype assembly.
- Flash checksum comparison. The extracted binary’s CRC is compared against any stored checksum in the bootloader region to confirm a clean read.
- Impedance-sensitive signal paths. For boards with USB, Ethernet, or RF traces, we apply impedance-controlled trace recovery techniques so that the cloned board’s signal integrity matches the original.
Authorization and Legal Framework
Every firmware and PCB copy bundle project requires documented proof of ownership or written authorization from the IP holder. We operate under project-specific NDAs, and our reverse engineering services page details the authorization workflow. Firmware extraction is performed strictly for authorized recovery—legacy maintenance, second-source manufacturing, or prototype reconstruction where the client owns the design.
Moving From Bundle to Production
Once you have the complete file set, the next step is often turnkey cloning and manufacturing. We can hand off Gerber, BOM, pick-and-place, and pre-programmed firmware images directly to our assembly partners, or package the files for your own CM. Either way, the bundle’s validation report gives your production team confidence that the first batch will boot.
Can you extract firmware if the MCU’s debug port is disabled?
In many cases, yes. Disabled JTAG/SWD does not always mean the flash is unreadable. Techniques like voltage-glitch attacks or UV exposure on older process nodes can bypass software read-protection. We assess each chip during the feasibility scan and quote accordingly. Hardware secure elements (TPMs, crypto co-processors) are a different matter—those are typically not recoverable.
Do I need to send more than one sample board?
One working sample is the minimum. A second board is helpful if the design uses buried vias or HDI microvias, because cross-sectioning (destructive) may be needed to confirm internal layer stackup. For simple 2–4 layer boards, one sample is usually sufficient.
What if the board has both an MCU and an FPGA?
FPGA bitstream extraction follows a different process than MCU firmware readout. If the bitstream is stored in an external SPI flash, we read that flash directly. If it is embedded in a volatile FPGA with encrypted configuration, recovery may not be feasible. We quote FPGA and MCU extraction as separate line items within the bundle.
How do you handle calibration or serial-number data stored in firmware?
Calibration tables and unique serial numbers are captured as part of the binary image. We flag these regions in the firmware map so your production team knows which addresses must be updated per-unit during programming. This prevents every cloned board from shipping with identical calibration values.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewWorking on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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