What Is Component Decapsulation?
Component decapsulation is the process of removing the molding compound, ceramic lid, or metal can that encases an integrated circuit, exposing the bare silicon die underneath. Engineers use it for failure analysis, die-level inspection, firmware readout on locked microcontrollers, counterfeit detection, and process characterization. The technique is destructive to the package but—when performed correctly—leaves the die and bond wires intact so the chip can still be probed, imaged, or even powered up for further testing.
Why Component Decapsulation Matters in Board-Level Projects
When a legacy board reaches end-of-life and the original firmware source is lost, or when a field failure needs root-cause analysis at the die level, there is no shortcut around opening the package. Component decapsulation bridges the gap between board-level troubleshooting and silicon-level evidence.
Common scenarios where our engineers perform decapsulation include:
- Firmware recovery — reading flash or EEPROM contents from a code-protected MCU after the package is opened and bond pads are exposed. See the full IC unlock process and methods for context on authorization requirements.
- Failure analysis — inspecting die-level defects such as electromigration voids, ESD damage craters (often < 5 µm), or bond-wire lift-off after thermal cycling.
- Counterfeit screening — verifying die markings, revision codes, and fab geometry against the datasheet to confirm authenticity before committing to a production run.
- Process benchmarking — measuring gate lengths, metal layer thicknesses, and passivation quality on a competitor or second-source part.
Component Decapsulation Methods Compared
No single method suits every package. The choice depends on package material, die size, the information you need afterward, and budget. Below is a practical comparison our lab uses when scoping a project.
| Method | Package Types | Typical Time | Die Survival Rate | Relative Cost |
|---|---|---|---|---|
| Chemical (hot acid) | Plastic QFP, SOIC, BGA, QFN | 15–90 min per device | 90–98 % | Low–Medium |
| Mechanical (grinding/milling) | Ceramic DIP, metal-can TO packages | 30–120 min | 80–95 % | Low |
| Laser ablation | Fine-pitch BGA, WLP, flip-chip | 10–45 min | 92–97 % | High |
| Plasma / dry etch | Specialty packages, MEMS lids | 1–4 hrs | 95–99 % | High |
Chemical Decapsulation (Hot Acid)
The most widely used approach. Fuming nitric acid (HNO₃, 90–98 % concentration) or sulfuric acid heated to 150–250 °C dissolves the epoxy mold compound while leaving the die, gold bond wires, and lead frame largely intact. The process requires precise temperature control: too cool and the acid stalls; too hot and it attacks the aluminum bond pads. On a standard 7 × 7 mm QFN we typically achieve full cavity exposure in 20–40 minutes with acid refreshed in two or three cycles.
Limitations: lead-free packages with silica-filled green mold compound dissolve more slowly. Copper bond wires (common since ~2010) are attacked by nitric acid, so a mixed-acid or jet-etch approach is needed to preserve them.
Mechanical Decapsulation
Grinding or CNC milling physically removes material from the top of the package. It works well on ceramic packages and metal cans where acid is ineffective or unnecessary. Our operators use a precision mill with a depth stop accurate to ±25 µm to avoid scoring the die surface. The trade-off is that bond wires near the cavity edge are at higher risk of mechanical damage.
Laser Ablation
A pulsed Nd:YAG or fiber laser selectively vaporizes mold compound in controlled layers. It excels on flip-chip BGAs where the die faces downward and acid access is poor. Laser decapsulation can target a specific area as small as 200 × 200 µm, which is useful when you only need to expose a single bond pad or fuse bank. Cost is roughly 2–3× chemical methods because of equipment time.
How Does a Typical Component Decapsulation Project Work?
Below is the workflow our lab follows. Turnaround from receipt of parts to delivery of a decapped device or die images is typically 3–7 working days, depending on complexity and queue depth.
- Intake & X-ray — We X-ray the device to map die position, wire bond layout, and lead-frame geometry before opening anything. This prevents blind cutting into the die.
- Method selection — Based on package type, mold compound, and the downstream goal (optical inspection, electrical probing, or firmware readout), we choose acid, mechanical, or laser.
- Decapsulation — Controlled removal of the encapsulant. For chemical work, the device sits in a heated acid well; acid is refreshed at timed intervals and progress is checked under a stereo microscope at 20–40× between cycles.
- Cleaning — Residual acid and debris are rinsed with acetone, IPA, and DI water in sequence. Ultrasonic cleaning at low power (40 kHz, < 30 s) removes stubborn particles without lifting bond wires.
- Inspection & imaging — Die surface is photographed at up to 1000× under a metallurgical microscope. SEM imaging is available when sub-micron features need documentation.
- Downstream work — If the goal is firmware recovery, the device is mounted on a custom probe card or socket adapter for electrical access. If it is part of a broader reverse engineering engagement, results feed into schematic or BOM reconstruction.
What Can Go Wrong — Failure Modes and Honest Limits
Component decapsulation is not risk-free. Clients should know the realistic constraints before committing devices:
- Bond-wire damage — Copper wires are thinner (18–25 µm) than gold wires (25–33 µm) and corrode in nitric acid within seconds of exposure. If the mold compound is not removed fast enough, wires can break. Success rate on copper-wire devices drops to ~85 % without jet-etch equipment.
- Die cracking — Thin dies (≤ 75 µm, common in stacked-die packages) are fragile. Thermal shock during acid heating or mechanical vibration during ultrasonic cleaning can crack them.
- Passivation attack — Over-etching dissolves the SiO₂/Si₃N₄ passivation layer, destroying surface features needed for optical analysis or probing.
- Incomplete exposure on multi-die modules — System-in-package (SiP) devices may have multiple dies at different depths. Exposing the bottom die usually sacrifices the top die.
We always recommend sending at least two samples when possible—one for the primary attempt and one as a backup. For single-sample, high-value parts, we run a trial on a same-family device (if available) before touching the target.
Component Decapsulation vs. Other IC Access Techniques
Decapsulation is not the only way to interact with a locked or failed IC. Understanding the alternatives helps you choose the right path. For a deeper comparison, see our guide on decapsulation vs. glitching and which method fits your chip.
| Technique | Destructive? | Best For | Typical Cost Range |
|---|---|---|---|
| Component decapsulation | Package yes, die usually no | Die inspection, bond-pad probing, firmware readout | $80–$500 per device |
| Voltage / clock glitching | No | Bypassing read protection on certain MCUs | $200–$2,000 per part number |
| Microprobing (FIB-assisted) | Partially | Accessing buried metal layers, editing fuses | $2,000–$10,000+ |
| Side-channel analysis | No | Extracting keys from crypto ICs | $3,000–$15,000+ |
When Decapsulation Feeds a Larger Board Copy Project
Component decapsulation rarely happens in isolation. It is usually one step in a chain: a legacy board needs cloning, a critical IC is code-locked, and the firmware must be recovered before the sample duplication build can be validated. Our workflow ties decapsulation results directly into the BOM and programming files so nothing falls through the cracks. If your project also requires bare-board data extraction, our chip decapsulation guide covers the IC-specific considerations in more detail.
Cost Factors for Component Decapsulation
Pricing depends on several variables. The table below gives ballpark ranges; exact quotes require knowing the part number and goal.
- Package type — Standard plastic SOIC/QFP: $80–$150. Large BGA (> 400 balls): $150–$350. Ceramic or metal-can: $100–$250.
- Quantity — Per-device cost drops 15–30 % on batches of 5+ identical parts.
- Downstream requirement — Decap-only (deliver the opened device) is cheapest. Decap + die photography + electrical probing adds $150–$400.
- Urgency — Standard 5–7 day turnaround vs. rush 2–3 day (30–50 % surcharge).
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewFrequently Asked Questions
Can a decapsulated IC still be powered up and tested?
Yes, in most cases. If the bond wires and die are intact after decapsulation, the device can be placed in a socket or on a probe station and powered normally. We routinely read firmware from decapped MCUs that are still electrically functional. The main risk is bond-wire damage during the process, which is why we X-ray first and monitor under a microscope between acid cycles.
How many sample devices should I send for component decapsulation?
We recommend a minimum of two: one primary and one backup. For high-value or irreplaceable parts, three is safer. If you have access to a same-family but different part number, sending that as a trial piece lets us dial in acid time and temperature before touching the target device.
Is component decapsulation legal?
Decapsulation itself is a standard laboratory technique used across the semiconductor industry for failure analysis, incoming inspection, and quality assurance. When used for firmware recovery, authorization and proof of ownership are required. We operate under NDA and require clients to confirm they hold rights to the IP being accessed. See our IC unlock overview for details on the authorization process.
What package types cannot be decapsulated?
Nearly all packages can be opened, but some are significantly harder. Hermetically sealed ceramic packages with brazed lids require mechanical removal. Wafer-level chip-scale packages (WLCSP) with no mold compound need laser or plasma techniques. Stacked-die packages can be partially decapped, but accessing the bottom die usually destroys the top die.
Related Services and Resources
- IC decapsulation — what determines if it is possible
- Reverse engineering complex motherboards
- Component sourcing and cross-referencing for board copy projects
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewWorking on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote