What Is Conformal Coating Removal and Why Does It Matter for Board Copy?
Conformal coating removal is the controlled stripping of a protective polymer layer—acrylic, silicone, urethane, epoxy, or parylene—from a populated PCB so that copper traces, component markings, and test points become accessible for scanning, probing, and reverse engineering. Without clean removal, optical scanners misread pad geometries, component reference designators stay hidden, and continuity probing becomes unreliable. Every accurate board copy project that starts with a coated sample must address this step first.
Why Boards Have Conformal Coating in the First Place
Conformal coatings protect assemblies from moisture, dust, thermal shock, and chemical exposure. They are standard on boards destined for automotive, aerospace, marine, industrial control, and outdoor telecom environments. Coating thickness typically ranges from 25 µm to 250 µm (1–10 mil), depending on the polymer and application method. IPC-A-610 Class 3 assemblies almost always carry some form of conformal coating.
The very properties that make coatings effective—chemical resistance, adhesion, optical opacity—are exactly what make them obstacles during reverse engineering. A 75 µm layer of urethane, for example, can obscure 0402 component markings entirely and add enough surface gloss to defeat automated optical inspection (AOI) reference scans.
Five Methods of Conformal Coating Removal
Our engineers select a removal method based on the coating chemistry, board complexity, and component sensitivity. Below is a decision-reference table we use internally.
| Method | Best For | Coating Types | Risk Level | Typical Time (per board) |
|---|---|---|---|---|
| Chemical solvent soak | Full-board strip of acrylic or urethane | AR, UR | Low–Medium | 15–60 min |
| Micro-abrasion / peeling | Localized access on silicone or acrylic | AR, SR | Low | 5–20 min per zone |
| Thermal burn-through | Spot access on thin acrylic | AR | Medium | 2–10 min per zone |
| Plasma etching | Parylene (XY) or very thin coatings | XY, AR | Low | 30–120 min (batch) |
| Mechanical scraping / grinding | Thick epoxy or potting compound edges | ER, potting | High | 20–90 min |
Chemical Solvent Soak
This is the most common approach for acrylic (AR) and urethane (UR) coatings. We use proprietary strippers that soften the polymer within 15–30 minutes without attacking solder joints or component bodies. The board is then rinsed in IPA and dried under warm air. Solvent soak works poorly on epoxy-based coatings (ER), which cross-link and resist most common solvents.
Micro-Abrasion and Peeling
Silicone coatings (SR) are rubbery and can often be peeled mechanically after a score line is cut with a scalpel. Micro-abrasion with a fine glass-bead pen at 1–2 bar pressure removes localized coating without disturbing 0.15 mm traces underneath—provided the operator controls dwell time. We use this method when only specific zones need to be exposed for probing, leaving the rest of the coating intact to protect components during handling.
Thermal Methods
A soldering station set to 300–350 °C can burn through thin acrylic coatings locally. This is a quick field technique but carries real risk: excessive heat can lift pads, reflow nearby solder joints, or damage temperature-sensitive components like electrolytic capacitors and MEMS sensors. Our lab uses this only on non-critical access points and never on BGA or QFN neighborhoods.
Plasma Etching
Parylene (XY) coatings are vapor-deposited and extremely uniform—typically 10–25 µm—but chemically inert to nearly all solvents. Oxygen plasma at 100–300 W etches parylene at roughly 0.5–1.0 µm per minute. A 20 µm parylene layer therefore requires 20–40 minutes of plasma exposure. This is the only reliable non-destructive method for parylene-coated boards, and it preserves all component markings.
Mechanical Scraping
Epoxy coatings and boards that have been partially potted sometimes require mechanical removal. This is the highest-risk method—carbide burrs and rotary tools can easily cut through solder mask and into copper. We reserve it for thick epoxy edges and transition zones, and always follow up with microscope inspection at 20× to verify trace integrity. When the entire board is encapsulated in hard potting compound, the scope expands to a full potting removal engagement.
How to Identify the Coating Type Before Removal
Choosing the wrong removal method damages boards. Identification is therefore the real first step. Here is how we classify coatings in the lab:
- Burn test (edge sample): Acrylic burns cleanly with a sweet smell; urethane chars and smells acrid; silicone leaves white ash.
- Solvent spot test: A drop of isopropyl alcohol softens acrylic within 30 seconds. Urethane resists IPA but responds to MEK. Epoxy and parylene resist both.
- Flexibility check: Silicone is rubbery and peelable. Acrylic is semi-rigid. Epoxy is hard and brittle.
- UV fluorescence: Many conformal coatings contain UV tracers per IPC-CC-830B. Under 365 nm UV, acrylic fluoresces blue-white, urethane yellow-green, and silicone varies by formulation.
We photograph every board under UV before starting removal. This map tells us where coating is present, where it is thin, and where it may have been applied unevenly—common on hand-dipped production boards.
What Can Go Wrong During Conformal Coating Removal
Conformal coating removal is not risk-free. Being transparent about failure modes is part of how we set expectations with clients:
- Component marking loss: Aggressive solvents or abrasion can erase silk-screen part numbers on ICs and passives. We photograph all markings at 10× magnification before any chemical contact.
- Pad lift: Thermal shock or mechanical force on aged FR-4 (especially boards older than 15 years) can delaminate pads. Risk increases on single-sided paper-phenolic boards.
- Solder joint disturbance: Solvents that attack flux residues can weaken marginal joints. We re-inspect all joints under microscope after stripping.
- Incomplete removal: Residual coating in via barrels or under low-standoff components (QFN, LGA) can block continuity probing. Ultrasonic agitation during solvent soak helps, but some residue may remain under 0.1 mm standoff parts.
On average, fewer than 2 % of boards we process suffer any visible damage during coating removal—and most of that is cosmetic marking loss, not functional trace damage. We always advise clients to send two samples when possible so one can serve as a reference if the other is compromised.
Conformal Coating Removal in Our Reverse Engineering Workflow
Coating removal sits at the very beginning of our PCB reverse engineering services. The sequence looks like this:
- Receive and photograph the coated board (visible light + UV).
- Identify coating type using the tests above.
- Strip coating using the matched method; rinse and dry.
- Post-strip inspection under microscope—verify markings, pad integrity, trace continuity.
- High-resolution optical scan of each layer (now unobstructed).
- Component cataloging for BOM generation.
- Schematic capture, Gerber extraction, drill file generation.
Skipping or rushing the coating removal step cascades errors downstream. Misread pad shapes produce incorrect footprints; hidden component values create BOM gaps; coating residue on via annular rings leads to false opens in netlist connectivity data. We allocate 1–4 hours specifically for coating removal and post-strip QC on every coated board, depending on complexity.
Special Cases: Selective Coating and Multi-Layer Coatings
Some boards carry selective conformal coating—applied only around connectors, high-voltage zones, or moisture-sensitive areas, leaving other regions bare. These are faster to process but require careful mapping so we do not apply solvent to uncoated areas where it could attack flux residues or labels.
Occasionally we encounter boards with two coating layers—for example, a silicone base coat under an acrylic top coat, or a parylene layer applied over urethane. Multi-layer coatings demand sequential removal: strip the outer layer first with its matched chemistry, then address the inner layer. This doubles processing time and requires re-identification between layers.
Cost and Turnaround Impact
Conformal coating removal typically adds $80–$250 to a circuit board copy engagement, depending on coating type, board size, and component density. Parylene removal is at the high end because it requires plasma equipment time. Acrylic solvent soak on a standard 100 × 160 mm board is at the low end.
Turnaround impact: expect 0.5–1 working day added for standard coatings, and 1–2 working days for parylene or multi-layer coatings. We quote this explicitly during feasibility review so there are no surprises.
Can I remove conformal coating myself before shipping the board?
You can, but we recommend against it unless you have identified the coating type and have the correct solvent. Incorrect removal attempts—especially mechanical scraping—frequently destroy component markings that we need for BOM generation. If you do strip the board, photograph all component markings first at high resolution and send the images with the board.
Does conformal coating removal damage the board permanently?
When performed correctly with the matched method, removal is non-destructive to copper, solder mask, and components. The coating itself is consumed. If you need the board returned in a functional state, let us know—we can re-coat it after reverse engineering is complete, though this is rarely requested.
What if only part of the board is coated?
Selective coating is common on automotive and industrial boards. We strip only the coated zones and leave bare areas untouched. This reduces cost and processing time. UV inspection reveals exactly where coating was applied.
Is epoxy conformal coating the same as potting compound?
Not exactly. Epoxy conformal coating is a thin (50–250 µm) layer applied by spray or dip. Potting compound fills an entire enclosure around the board, often several millimeters thick. Potting removal is a separate, more involved process that may require CNC milling. See our potting removal process guide for details.
Can you reverse-engineer a board without removing the coating?
In limited cases—if the coating is very thin, transparent, and component markings are legible—we can scan through it. But probing for continuity verification and reading obscured reference designators almost always require at least partial removal. We evaluate this during feasibility review and advise accordingly.
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