What Is Copper Pour Recovery?
Copper pour recovery is the process of extracting every filled-copper region—ground planes, power planes, split pours, and partial fills—from a physical printed circuit board and converting them into editable, fabrication-ready Gerber or ODB++ data. Our engineers use high-resolution imaging, cross-sectioning, and impedance-aware reconstruction to reproduce pour boundaries within ±1 mil (0.025 mm) of the original design, including thermal reliefs, anti-pad clearances, and keep-out zones that are invisible in a simple photograph.
Why Copper Pours Are the Hardest Layer to Recover
Traces and pads are discrete objects with clear edges. Pours are the opposite: they fill every remaining gap on a layer, conforming to hundreds of clearance rules simultaneously. When the original CAD data is lost, three problems make recovery difficult.
- Hidden geometry. Inner-layer pours on a 4-, 6-, or 12-layer board are buried under laminate. Non-destructive X-ray or CT scanning is required, and even then, resolution limits can blur pour-to-clearance transitions at pitches below 6 mil.
- Thermal relief ambiguity. A four-spoke thermal relief looks different from a direct connect, but etching tolerances, solder wicking, and oxidation can make them hard to distinguish on an aged board. Misidentifying a thermal as a direct connect (or vice versa) changes both the electrical netlist and the solderability of the rebuilt board.
- Split-plane boundaries. Power planes often carry multiple voltage rails separated by thin isolation gaps (8–15 mil typical). These gaps can be obscured by prepreg squeeze-out or micro-cracking on boards that have been in service for 10+ years.
How We Perform Copper Pour Recovery
Step 1 — Layer Imaging
External layers are photographed at 2400 dpi minimum under controlled lighting. Internal layers are imaged via micro-focus X-ray (resolution down to 0.5 mil) or, when X-ray contrast is insufficient, progressive de-lamination under a stereo microscope. Each layer image is calibrated against at least four fiducial points to correct for lens distortion.
Step 2 — Pour Boundary Extraction
Using bitmap-to-vector conversion software (typically Altium, PADS, or proprietary tools), the engineer defines pour outlines. Automatic edge detection handles roughly 70–80 % of the boundary, but every thermal relief, anti-pad, and isolation gap is verified manually. On a typical 4-layer board with two pour layers, this step alone takes 4–8 hours.
Step 3 — Rule Reconstruction
Rather than storing the pour as a raw polygon (which can be hundreds of megabytes for a dense board), our team reverse-engineers the original design rules—clearance to trace, clearance to pad, thermal spoke width, thermal gap—and rebuilds the pour parametrically. This means the recovered Gerber behaves correctly if a fab house re-panelizes or a downstream engineer makes minor ECO changes.
Step 4 — Netlist Verification
The recovered pour is assigned to the correct net (GND, VCC, 3V3, etc.) and checked against the continuity data measured from the physical board. Any net mismatch flags an error that is resolved before sign-off. We cross-check against the recovered schematic when one is part of the project scope.
Step 5 — DRC and Deliverable Export
Final design-rule checks confirm minimum copper-to-edge clearance (typically ≥ 10 mil), annular ring compliance per IPC-2221, and impedance targets for controlled-impedance pours. Deliverables are exported as Gerber RS-274X, ODB++, or native Altium/KiCad files per the client’s preference.
Typical Tolerances and Constraints
| Parameter | Typical Recovered Accuracy | Notes |
|---|---|---|
| Pour boundary position | ±1 mil (±0.025 mm) | External layers; inner layers ±1.5 mil via X-ray |
| Thermal relief spoke width | ±0.5 mil | Measured under 50× magnification |
| Isolation gap (split plane) | ±1 mil | Gaps < 6 mil may require cross-section confirmation |
| Anti-pad clearance | ±1 mil | Verified against pad stack for each via class |
| Copper weight identification | Exact (1 oz, 2 oz, 3 oz+) | Measured by micrometer on cross-section |
For boards with heavy copper planes (3 oz or above), etch compensation factors are applied to the recovered data so the fabricated copy matches the original current-carrying capacity.
What Can Go Wrong — Honest Failure Modes
We recover pours successfully on the vast majority of boards, but there are real limits.
- Severely corroded inner layers. If a board has been exposed to moisture or chemical contamination for years, copper dissolution can erase pour boundaries entirely. Recovery accuracy drops to ±3–5 mil in corroded zones, and some boundaries may need to be inferred from the netlist rather than directly observed.
- Blind/buried via pours on 12+ layer HDI. Stacked microvias with pour fills on sequential-lamination layers require CT scanning at sub-mil resolution. Turnaround and cost increase significantly—budget 3–5 additional working days per HDI stackup.
- Intentional hatched pours. Some RF and flex designs use hatched (cross-hatch) fills instead of solid pours. Recovering hatch pitch, line width, and angle adds complexity. Expect 20–30 % more engineering time compared to solid-pour recovery.
Copper Pour Recovery as Part of a Full Board Copy
Pour recovery is rarely a standalone task. It is one deliverable within a broader reverse engineering engagement that also produces trace routing, pad stacks, drill data, and a BOM. Here is how the pour data integrates with the rest of the package:
- Gerber set: Each pour layer is a separate Gerber file (e.g., GND.gbr, PWR.gbr), merged with trace layers during panelization.
- Drill data: Via anti-pads in the pour must align with the NC drill file to within ±0.5 mil. Misalignment causes annular-ring violations or, worse, shorted planes.
- Assembly data: Thermal reliefs directly affect solderability. The pour data feeds into the pick-and-place and assembly documentation, ensuring reflow profiles match the thermal mass of the original board.
Who Needs Copper Pour Recovery?
Legacy Equipment Owners
When the OEM is defunct and spare boards are unavailable, recovering the copper pours is the first step toward fabricating an exact replacement. This is common in industrial control systems where a single board failure can shut down a production line.
Product Redesign Teams
Engineers migrating a proven design to a new form factor need the original pour structure as a starting point. Parametric pour data (not just raw polygons) lets them re-pour around a modified component layout while preserving impedance and EMI shielding characteristics.
Quality and Failure-Analysis Labs
Comparing a failed board’s pour geometry against the recovered “golden” reference highlights manufacturing defects—missing thermal reliefs, insufficient clearance, or pour voids—that would be invisible without accurate baseline data.
Turnaround and Pricing Signals
| Board Complexity | Pour Layers | Typical Turnaround | Price Range (Pour Recovery Only) |
|---|---|---|---|
| 2-layer, single GND pour | 1 | 2–3 working days | $150–$300 |
| 4-layer, GND + PWR | 2 | 3–5 working days | $300–$600 |
| 6–8 layer, split planes | 3–4 | 5–8 working days | $600–$1,200 |
| 10–16 layer HDI, hatched or heavy copper | 4–8 | 8–15 working days | $1,200–$2,500+ |
These ranges cover pour recovery as a line item. A complete board duplication project bundles pour recovery with trace extraction, BOM, drill, and assembly files at a lower combined cost than ordering each deliverable separately.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewFrequently Asked Questions
Can copper pours be recovered without destroying the board?
Yes, for most boards. External-layer pours are photographed non-destructively. Inner-layer pours are recovered via X-ray or CT scan. Destructive de-lamination is used only when X-ray contrast is too low—typically on boards thicker than 3 mm with heavy copper or embedded components. We always confirm the approach with the client before cutting.
How do you distinguish a ground pour from a power pour on an inner layer?
We probe the physical board with a multimeter or flying-probe tester to identify net assignments before imaging. Each plane’s net is confirmed by continuity to known pins (e.g., decoupling-cap pads, connector ground pins). The result is cross-referenced with the recovered schematic when available.
What file formats do you deliver the recovered pour data in?
Standard delivery is Gerber RS-274X (one file per pour layer) plus an Excellon drill file with matching anti-pads. We also deliver native Altium .PcbDoc, KiCad .kicad_pcb, or ODB++ on request at no extra charge.
Does pour recovery include impedance matching?
If the original board uses controlled-impedance pours (common in RF, DDR, and high-speed digital designs), we measure the stackup cross-section and calculate the impedance profile. The recovered pour geometry and dielectric spacing are adjusted so the fabricated copy meets the same impedance targets, typically 50 Ω single-ended or 100 Ω differential ±10 %.
What if some pour areas are too damaged to read?
We flag ambiguous zones in the deliverable and provide two options: infer the boundary from surrounding clearance rules and netlist logic, or leave the zone marked as “engineer review required.” Most clients choose inference, which succeeds in roughly 95 % of cases based on our project history.
Working on a board like this?
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