What Is a Free PCB Sample Evaluation?
A free PCB sample evaluation is a no-cost, no-obligation assessment our engineers perform on your physical board or high-resolution scans before any project begins. Within 2–5 working days we report back with a feasibility verdict, a risk profile, an estimated layer count, IC-protection status, and a realistic price range—so you know exactly what you are getting into before spending a dollar.
Most boards we receive fall into one of three buckets: straightforward clones that can ship Gerbers in under two weeks, moderate-complexity jobs with protected MCUs or 6+ layers that need extra lab time, and edge cases where potting compound, custom ASICs, or BGA-only routing push turnaround past 30 days. The evaluation tells you which bucket your board sits in—and whether the project makes financial sense at all.
Why Request a Sample Evaluation Before Committing?
Reverse-engineering quotes without hands-on inspection are guesses. A board photograph cannot reveal buried vias on layer 3, an RDP-Level-2 STM32, or a corroded ground plane under a shielding can. Our evaluation eliminates that uncertainty.
- Cost clarity: We provide a price range accurate to ±15 %, not a vague “depends on complexity.”
- Risk transparency: If an IC is locked at a level we cannot reliably defeat, we say so upfront rather than billing hours first.
- Timeline realism: You get a working-day estimate—typically 5–8 days for 2-layer boards, 12–20 days for 6–10 layers, 25+ days for HDI or 12+ layer stacks.
- Go / no-go confidence: About 8 % of boards we evaluate are not economically viable to clone. Knowing that before you ship 50 units saves real money.
If you are unsure who actually benefits from reverse engineering, the evaluation itself will answer that question for your specific situation.
What Do Our Engineers Check During the Evaluation?
The evaluation is structured, not a casual glance. Here is exactly what we inspect and report on:
| Check | What We Look For | Why It Matters |
|---|---|---|
| Layer count estimate | Via structure, edge cross-section, board thickness vs. copper weight | Determines delayering steps and cost multiplier |
| IC inventory | Part numbers, packages, manufacturer datasheets, obsolescence status | Identifies sourcing risk and firmware-readout feasibility |
| MCU protection level | Read-protection fuses, OTP vs. flash, bond-wire configuration | Tells us if firmware recovery is realistic or blocked |
| Board condition | Corrosion, heat damage, lifted pads, missing components | Damaged reference boards increase error risk |
| Potting / conformal coat | Compound type, coverage area, adhesion to components | Potted boards need chemical or mechanical removal—adds 3–7 days |
| Signal integrity concerns | Impedance-controlled traces, differential pairs, RF sections | Requires impedance stackup matching, not just copper tracing |
| BOM complexity | Unique part count, custom/proprietary components, end-of-life ICs | Drives procurement cost and lead time |
For boards encased in resin, we outline the removal method and associated risks—something we cover in depth in our guide on reverse-engineering potted boards.
How the Evaluation Process Works Step by Step
Step 1 — Ship or Upload
Send us one physical sample board, or upload 600+ DPI scans of both sides plus close-ups of every IC marking. Physical boards yield more accurate results because we can measure board thickness (±0.05 mm) and probe test points. International shipping typically takes 3–5 days via DHL or FedEx; we cover return shipping on boards we accept for a full project.
Step 2 — Initial Triage (Day 1)
An engineer logs the board, photographs it under magnification, catalogs all visible ICs, and checks part numbers against our internal database of 4,000+ previously evaluated MCUs. If we have worked with the same chip family before, feasibility feedback can come within 24 hours.
Step 3 — Deep Inspection (Days 2–4)
We perform a non-destructive layer-count estimate using via analysis and, when needed, an edge micro-section. We cross-reference the MCU against known protection levels. For example, an STM32F1 at RDP Level 1 is recoverable in most cases, while RDP Level 2 on an STM32F4 is a different conversation entirely—something we detail in our STM32 unlock feasibility guide.
Step 4 — Evaluation Report (Day 3–5)
You receive a written report covering: feasibility (go / conditional / no-go), estimated layer count, IC protection summary, risk factors, deliverable list (Gerber, schematic, BOM, firmware), price range, and estimated turnaround in working days. No invoice is attached. If you decide not to proceed, we return the board at no charge.
Before shipping, review our PCB copy checklist to make sure you include everything we need for the fastest possible assessment.
What Does the Evaluation Report Look Like?
Below is a simplified version of the summary table included in every report:
| Parameter | Finding |
|---|---|
| Board dimensions | 112 × 78 mm, 1.6 mm thickness |
| Estimated layers | 4 (2 signal + 2 plane) |
| Unique component count | 47 line items |
| Critical IC | STM32F103RCT6 — RDP Level 1, recoverable |
| Board condition | Good — minor oxidation on edge connector, no lifted pads |
| Risk level | Low |
| Deliverables | Gerber (RS-274X), schematic (PDF + Altium), BOM (Excel), firmware (.bin) |
| Price range | $850–$1,100 |
| Turnaround estimate | 10–14 working days after approval |
The actual report includes IC-by-IC notes, high-resolution board photos with annotations, and a risk-mitigation plan for any conditional items. If a 4-layer board copy is straightforward, the report is concise. For 10+ layer HDI stacks, expect two to three pages of detail.
Common Evaluation Outcomes — And What They Mean for You
Go (≈ 72 % of boards)
The board is technically and economically viable. We provide a firm quote, and work begins once you approve. Typical boards in this category: 2–6 layer FR-4, unprotected or lightly protected MCUs, standard components still in production.
Conditional (≈ 20 % of boards)
Feasible with caveats. Examples: an MCU with uncertain protection that requires a test decap, an obsolete op-amp that needs a cross-reference substitute, or a partially damaged reference board where we may need a second sample. We quote the base price plus a contingency line item.
No-Go (≈ 8 % of boards)
The project is not viable at a reasonable cost. Typical reasons: custom ASIC with no available die-level documentation, heavily fused FPGA bitstream with no readback path, or a board so damaged that critical routing is unrecoverable. We explain why and, where possible, suggest alternatives such as reverse engineering for repair instead of full cloning.
What Does “Free” Actually Mean?
There is no hidden evaluation fee, no deposit, and no obligation. You pay nothing unless you approve a full project quote. We absorb the engineering time because roughly three out of four evaluations convert to projects—and because an honest upfront assessment builds the trust that makes long-term client relationships work. We do ask that you ship the board at your own cost; we handle return shipping.
Our full process overview walks through every stage from evaluation to final deliverable handoff.
Frequently Asked Questions About Free PCB Sample Evaluation
How long does a free PCB sample evaluation take?
Most evaluations are completed in 2–5 working days after we receive the board. Simple 2-layer boards with common ICs often get a same-day or next-day preliminary verdict. Complex boards with potting compound or 8+ layers may take the full five days due to additional inspection steps.
Can I send photos instead of a physical board?
Yes, but accuracy drops. High-resolution scans (600 DPI minimum, both sides, plus macro shots of every IC marking) let us give a preliminary feasibility opinion. However, we cannot confirm layer count, measure board thickness, or probe test points from images alone. A physical sample always produces a more reliable evaluation.
Is my board safe during the evaluation?
The evaluation is non-destructive. We do not delayer, decap ICs, or desolder components at this stage. The board is returned in the same condition it arrived. If destructive steps are needed later (e.g., cross-sectioning for layer verification), we request written approval first.
What if the evaluation says “no-go”?
We return your board at no charge and provide a written explanation of the technical barriers. In some cases we suggest partial recovery options—extracting only the schematic, or sourcing a functional replacement IC—so the project is not a total loss.
Do you sign an NDA before evaluation?
Yes. We execute a mutual NDA before any board ships. All evaluation data, photographs, and IC findings are treated as confidential and stored on encrypted internal servers. We never share board details with third parties.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewWorking on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote