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HDI PCB Copy Guide | Microvias, Stacked Vias & Layers

Oct 1, 2026  /  PCB COPY

hdi pcb copy guide: Cross-section of an HDI PCB revealing stacked microvias and build-up layers under a microscope

HDI PCB Copy Guide: What It Takes to Reverse-Engineer High-Density Interconnect Boards

An HDI PCB copy guide must address the structures that make HDI boards fundamentally harder to clone than standard multilayer designs: laser-drilled microvias (typically 75–150 µm), stacked or staggered via columns, and sequential lamination build-up layers that cannot be imaged in a single cross-section. Our engineers treat every HDI copy as a multi-phase reconstruction—optical imaging, micro-sectioning, impedance modelling, and netlist verification—because skipping any phase produces Gerber files that look correct but fail electrically or cannot be fabricated.

Why HDI Boards Are Harder to Copy Than Standard Multilayer PCBs

hdi pcb copy guide: Cross-section of an HDI PCB revealing stacked microvias and build-up layers under a microscope

Standard 4–8 layer boards use through-hole vias visible from both sides. HDI boards break that assumption. A typical 10-layer 2+N+2 build-up uses blind microvias on layers 1–2 and 9–10, buried vias on layers 3–8, and possibly stacked via pillars connecting all ten layers. Each via type has a different drill diameter, aspect ratio, and annular ring spec.

The practical consequence: you cannot simply photograph each layer, auto-trace it, and stitch the result. Layer registration shifts during sequential lamination, microvia capture pads are as small as 200 µm (8 mil), and copper fill patterns on inner layers obscure via landing targets. Without controlled cross-sectioning, the via stack architecture is essentially invisible.

Common HDI Structures We Encounter

Structure Typical Drill ∅ Aspect Ratio Capture Pad Copy Difficulty
Blind microvia (L1–L2) 75–100 µm 0.5:1 – 0.8:1 200–250 µm Moderate
Stacked microvia (L1–L3) 75–100 µm per step ≤1:1 per step 250–300 µm High
Staggered microvia 75–125 µm ≤1:1 per step 250–350 µm High
Buried via (core layers) 150–250 µm ≤8:1 300–450 µm Moderate
Through-hole via 200–350 µm ≤10:1 400–600 µm Low
Via-in-pad (filled/capped) 100–200 µm varies per BGA pitch High

Step-by-Step HDI PCB Copy Process

1. Non-Destructive Imaging

We start with high-resolution optical scans of both outer layers (2400+ DPI) and X-ray imaging to map internal via locations without destroying the board. X-ray gives us a density map of drill hits, but it cannot resolve individual layer connections on a stacked-via column—that requires sectioning.

2. Controlled De-Layering

Each build-up layer is chemically or mechanically removed in sequence. For a 2+N+2 board, we strip the outer prepreg and image layers 2 and 9 before touching the core. Registration marks are captured at every step; drift of even 25 µm (1 mil) accumulates across layers and breaks pad-to-via alignment in the Gerber output.

3. Microvia Mapping and Cross-Sectioning

Microvias that appear as simple dots on an X-ray may be blind, stacked two-deep, or staggered. We take at least three microsection cuts per board—at high-density BGA fanout areas—to confirm the via stack architecture. The cross-section reveals copper fill quality, dielectric thickness per layer (critical for impedance), and whether vias are filled with conductive or non-conductive paste.

4. Trace and Space Extraction

HDI designs routinely use 3/3 mil (75/75 µm) trace/space on outer layers and 3.5/3.5 mil on inner layers. Our extraction pipeline uses calibrated optical comparison against a known scale to hold ±0.5 mil accuracy. Any trace narrower than 2.5 mil triggers a manual verification pass, because fabrication yield below that threshold drops sharply.

5. Stackup Reconstruction and Impedance Modelling

From the cross-sections we extract dielectric thickness (often 60–100 µm per build-up layer vs. 200+ µm for a standard core), copper weight per layer (typically ½ oz on HDI layers, 1 oz on core layers), and material type (usually high-Tg FR-4 or Megtron 6 for ≥10 Gbps signals). We reconstruct the stackup in a 2D field solver and verify that differential pairs hit the target impedance—100 Ω ±10% for most USB/PCIe/LVDS nets.

6. Netlist Verification

The extracted Gerber set is run through a DRC and then a full netlist comparison against the original board’s continuity test. Every microvia connection is verified. On a recent 12-layer smartphone RF module, this step caught seven staggered vias that had been misclassified as stacked—an error that would have created open circuits on three power rails.

How Does Drill Aspect Ratio Affect an HDI Copy?

Drill aspect ratio—the ratio of board or layer thickness to drill diameter—is the single most important manufacturability constraint in an HDI copy. If your reconstructed Gerber specifies a 100 µm via through a 1.0 mm laminate (10:1 ratio), most HDI fabricators will reject it; their process limit is typically 8:1 for mechanical drills and 1:1 per laser step for microvias. An incorrect aspect ratio in the output files means the copy cannot be built, regardless of how accurate the trace extraction was.

Use the checker below to validate your via geometry before requesting a quote:

PCB manufacturing

Drill Aspect Ratio Checker

Board thickness divided by hole diameter decides whether a hole is routine, expensive, or a conversation with your fabricator.

mm
mm
mm
Aspect ratio — :1
Manufacturability —
Smallest drill at 10:1 — mm
Thickest board at 10:1 — mm
Expected plating uniformity —
How this is calculated

Aspect ratio is board thickness / finished hole diameter for a through hole, and via depth / via diameter for a blind or buried via. Electroplating chemistry has to circulate down the barrel, and it gets harder to keep copper thickness uniform as the hole gets deeper and narrower.

Working guidance for a standard shop: up to 8:1 is routine, 8:1 to 10:1 is available almost everywhere at normal pricing, 10:1 to 12:1 needs a capable fabricator and costs more, and beyond 12:1 you are into specialist processes. Laser blind vias run to a different rule entirely, usually 0.75:1 to 1:1, which is why HDI boards use stacked or staggered microvias instead of one deep hole.

Enter your drill diameter and the dielectric thickness the via must traverse. If the result exceeds 1:1 for a single laser step or 8:1 for a mechanical through-hole, the design needs a stacked or staggered approach—or a thinner core. Our engineers flag these constraints automatically during every HDI and multilayer layout copy project.

Build-Up Layer Configurations We Handle

HDI boards are classified by their build-up structure. The notation “2+N+2” means two sequential build-up layers on each side of an N-layer core. Here is what each configuration demands during a copy:

Configuration Total Layers (typical) Microvia Steps Copy Turnaround* Key Challenge
1+N+1 6–8 1 per side 8–12 days Single blind via; straightforward sectioning
2+N+2 8–12 2 per side 12–18 days Stacked vs. staggered ambiguity
3+N+3 12–16 3 per side 18–25 days Via column integrity; very thin dielectrics
ELIC (Every Layer Interconnect) 10–20 All layers 20–30+ days Full stacked columns; highest registration demand

*Working days for Gerber + BOM + schematic delivery. Expedited timelines available for 1+N+1 and 2+N+2 builds.

What Deliverables Come Out of an HDI Copy?

Engineer scanning a de-layered HDI board with an optical imaging system

An HDI board copy produces the same deliverable set as any board copy, but with additional HDI-specific documentation:

  • Gerber RS-274X / ODB++ — every layer, including separate drill files for each via type (laser blind, laser buried, mechanical through)
  • Stackup drawing — layer-by-layer dielectric thickness, copper weight, material callout, impedance targets
  • Bill of Materials — cross-referenced to distributor part numbers where possible
  • Schematic (optional) — reverse-engineered from netlist; essential if you plan layout modification later
  • Pick-and-place file — component X/Y/rotation for automated assembly
  • Impedance report — simulated vs. target for every controlled-impedance net class

For a full breakdown of what ships with a completed project, see our complete deliverables list.

Failure Modes: What Goes Wrong in HDI Copies

Honesty matters more than marketing. Here are the most common failure modes we see—both in our own early work and in files clients bring us from other vendors:

  • Stacked-via misidentification. X-ray alone cannot distinguish a true stacked column from two offset staggered vias. The fix: microsection at BGA breakout zones.
  • Impedance drift from wrong dielectric thickness. A 10 µm error in a 65 µm build-up layer changes impedance by ~8%. The fix: measure at three or more cross-section points and average.
  • Annular ring violation. Shrinking the capture pad by even 1 mil on a 200 µm pad can push it below IPC-6012 Class 3 minimum (50 µm annular ring). The fix: enforce DRC rules matched to the target fab’s capability.
  • Drill file confusion. Merging laser and mechanical drill hits into a single file causes the fabricator to drill all holes at one diameter. The fix: separate drill files per via type, clearly labeled.

When Should You Request an HDI Copy vs. a Redesign?

Not every project needs a 1:1 copy. If the original board uses a 3+N+3 build-up but your production volumes are low (<500 units), it may be more cost-effective to redesign for fewer build-up layers—dropping from 3+N+3 to 2+N+2 can cut bare-board cost by 30–40%. We evaluate this during feasibility review and recommend the lower-cost path when it does not compromise electrical performance.

Conversely, if you need an exact functional clone for legacy equipment support or regulatory compliance (same form factor, same connectors, same test points), a faithful HDI copy is the right path. Our reverse engineering team handles both scenarios.

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Frequently Asked Questions

Can you copy an HDI board from just one sample?

Yes, for most 1+N+1 and 2+N+2 designs a single sample is sufficient. For 3+N+3 or ELIC boards, we strongly recommend two samples—one for imaging and one for destructive cross-sectioning—because the de-layering process is irreversible and a second sample lets us verify ambiguous via stacks independently.

What is the minimum trace/space you can extract accurately?

We reliably extract 3/3 mil (75/75 µm) trace and space with ±0.5 mil accuracy. Below 2.5/2.5 mil we can still extract geometry, but we flag those features for manual verification and recommend the client confirm with their fabricator’s capability sheet before ordering boards.

How do you handle via-in-pad under BGA components?

We X-ray the BGA area first to map via locations under each ball. After component removal (hot-air or IR reflow), we image the exposed pads and cross-section at least two via-in-pad locations to confirm fill type (copper-filled, epoxy-filled, or capped). The drill file specifies filled vias so the fabricator applies the correct process.

Do you copy the firmware or ICs on HDI boards?

Board-level copy covers the physical PCB: Gerber, BOM, stackup, and schematic. IC-level firmware extraction is a separate authorized service requiring proof of IP ownership. If you need both, contact us and we will scope them together under NDA.

What file formats do you deliver?

Standard delivery includes Gerber RS-274X (or ODB++ on request), Excellon drill files (separate per via type), BOM in Excel, schematic in PDF and editable format (Altium/KiCad/OrCAD per your preference), and a stackup specification sheet. See the full deliverables page for details.

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