HDI PCB reverse engineering is the process of deconstructing a high-density interconnect board—layer by layer—to extract complete Gerber data, a net-verified schematic, and a bill of materials. Because HDI designs pack microvias (typically 75–100 µm drill), stacked or staggered via structures, and trace/space as tight as 50/50 µm (≈ 2/2 mil), the work demands specialized cross-sectioning, high-resolution imaging at 2400+ DPI, and impedance-aware stackup reconstruction that standard PCB copying workflows cannot deliver.
What Makes HDI PCB Reverse Engineering Harder Than Standard Boards?
A conventional 4- or 6-layer FR-4 board uses through-hole vias with 0.3 mm drills and 150 µm (6 mil) trace/space. HDI boards break every one of those assumptions:
- Microvia layers: Laser-drilled vias 75–125 µm in diameter connect only adjacent layers, making them invisible from the surface unless imaged after controlled delamination.
- Stacked & staggered vias: A 2+N+2 or 3+N+3 buildup can hide 4–6 sequential via transitions inside the laminate. Missing even one collapses the entire netlist.
- Fine-pitch fan-out: BGA packages at 0.4 mm pitch require dog-bone fan-out patterns with 50 µm traces—below the optical resolution of many flatbed scanners used for basic PCB copying.
- Impedance-critical stackups: HDI boards in 5G, medical, and automotive applications often specify controlled impedance on multiple layer pairs, with dielectric thicknesses of 50–75 µm. Recovering the stackup wrong means the clone won’t pass signal-integrity validation.
These factors combine to make HDI reverse engineering roughly 2–3× more labor-intensive than an equivalent-layer-count non-HDI board.
Our HDI PCB Reverse Engineering Process
Step 1 — Incoming Inspection & Non-Destructive Imaging
We photograph both sides at 4800 DPI, X-ray the board to map buried and blind via locations, and run an initial component inventory. X-ray is critical for HDI: it reveals stacked via columns and internal pad sizes that surface inspection misses entirely.
Step 2 — Controlled Layer-by-Layer Delamination
Each buildup layer is separated using precision CNC milling and chemical delamination. For a 10-layer 2+N+2 HDI board, this yields 10 copper images plus dielectric thickness measurements at multiple points across the panel. We record dielectric values to ±5 µm for impedance reconstruction.
Step 3 — High-Resolution Scanning & Vectorization
Individual copper layers are scanned at 2400–4800 DPI depending on minimum feature size. Our vectorization software converts raster images to Gerber RS-274X with pad-to-trace alignment accuracy of ±0.5 mil (12.7 µm). Microvia pads are verified against the X-ray dataset to ensure correct layer-pair assignment.
Step 4 — Netlist Extraction & Schematic Generation
The Gerber set is loaded into EDA tools for automated netlist extraction. Every net is cross-checked against the physical board using continuity testing on a sample of critical nets (power rails, high-speed differential pairs, clock lines). The schematic is drawn hierarchically, grouping by functional block.
Step 5 — Stackup & Impedance Reconstruction
Using the measured dielectric thicknesses, copper weights, and known laminate material (often Megtron 6, IS415, or standard high-Tg FR-4), we reconstruct the full impedance-controlled stackup. Single-ended and differential impedance targets are back-calculated and documented. If you’re working with boards that use high-Tg laminate systems, our process accounts for their specific Dk/Df values.
Step 6 — Drill Aspect Ratio & Via Feasibility Verification
HDI fabrication is constrained by via aspect ratios. Microvias are typically limited to 0.8:1 to 1:1 (depth:diameter), while mechanical through-holes max out around 10:1 for standard fabs and 12:1 for advanced shops. We verify every via in the recovered design against these limits before releasing Gerber files.
Use our drill aspect ratio checker below to verify whether your HDI via geometries are within manufacturable limits:
PCB manufacturing
Drill Aspect Ratio Checker
Board thickness divided by hole diameter decides whether a hole is routine, expensive, or a conversation with your fabricator.
How this is calculated
Aspect ratio is board thickness / finished hole diameter for a through hole, and via depth / via diameter for a blind or buried via. Electroplating chemistry has to circulate down the barrel, and it gets harder to keep copper thickness uniform as the hole gets deeper and narrower.
Working guidance for a standard shop: up to 8:1 is routine, 8:1 to 10:1 is available almost everywhere at normal pricing, 10:1 to 12:1 needs a capable fabricator and costs more, and beyond 12:1 you are into specialist processes. Laser blind vias run to a different rule entirely, usually 0.75:1 to 1:1, which is why HDI boards use stacked or staggered microvias instead of one deep hole.
Enter your via diameter and board (or layer-pair) thickness. A result exceeding 1:1 for microvias or 10:1 for mechanical drills flags a potential fabrication constraint that our engineers will address in the recovered stackup.
HDI Stackup Types We Reverse Engineer
| Stackup Type | Typical Layer Count | Via Structure | Common Applications | Reverse Engineering Complexity |
|---|---|---|---|---|
| 1+N+1 | 4–8 | Single blind microvia + PTH core | Smartphones, wearables | Moderate |
| 2+N+2 | 8–12 | Stacked/staggered microvias + PTH | 5G modules, SSD controllers | High |
| 3+N+3 | 12–18 | 3 sequential microvia layers + buried vias | FPGA carriers, networking ASICs | Very high |
| ELIC (Every Layer Interconnect) | 10–20 | Copper-filled stacked microvias on every layer | Advanced AP/SoC substrates | Extreme |
For boards with dense BGA fan-out routing, we use dedicated BGA decapping and pad-mapping procedures to capture every breakout trace accurately.
Deliverables
- Gerber RS-274X — full layer set including paste, mask, silkscreen, drill files (Excellon), and an IPC-2581 stackup drawing.
- Schematic — hierarchical, in Altium .SchDoc, KiCad, or PDF format.
- BOM — component values, packages, manufacturer part numbers (cross-referenced where originals are obsolete).
- Impedance report — target Z₀ and Zdiff per layer pair, dielectric constants, copper weights.
- Assembly drawing — component placement coordinates and polarity marks.
What Does HDI PCB Reverse Engineering Cost?
Pricing depends on layer count, via complexity, board area, and BOM size. Below are representative starting ranges:
| Board Profile | Layers | Estimated Cost (USD) | Lead Time (Working Days) |
|---|---|---|---|
| Simple HDI (1+N+1), ≤ 100 cm² | 6–8 | $1,200 – $2,500 | 10–12 |
| Mid-complexity (2+N+2), ≤ 150 cm² | 10–12 | $2,800 – $5,500 | 12–15 |
| High-complexity (3+N+3 / ELIC), >150 cm² | 14–20 | $5,500 – $12,000+ | 15–22 |
These ranges assume a single sample board provided. Rush service (5–8 day turnaround) adds 30–50%. For a detailed quote, our experienced reverse engineering team can evaluate your board within 24 hours.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewCommon Failure Modes & How We Avoid Them
HDI reverse engineering has specific pitfalls that less experienced shops hit regularly:
- Microvia misassignment: A blind via from L1→L2 looks identical to one from L1→L3 on a surface scan. We cross-reference X-ray depth data with delamination results to assign every via to its correct layer pair.
- Stacked via column breaks: If copper fill in a stacked via is incomplete, continuity testing may pass while the recovered Gerber incorrectly shows a full stack. We microsection at least 3 via columns per board to verify fill quality.
- Impedance mismatch on clone: Using generic FR-4 Dk (4.2–4.5) instead of the actual laminate’s Dk (e.g., Megtron 6 at 3.71 @ 1 GHz) will shift impedance by 8–12%. We identify the laminate brand from cross-section color, texture, and Dk measurement.
- Fine-pitch trace bridging: At 50 µm trace/space, a 0.5 mil vectorization error can merge adjacent traces. Our dual-pass verification—automated DRC plus manual spot-check on every BGA fan-out zone—catches these before file release.
Who Needs HDI PCB Reverse Engineering?
The most common scenarios our engineers encounter:
- Legacy equipment support: OEM no longer supplies replacement boards; the original design files were never transferred. Common in medical devices and industrial automation.
- Second-source qualification: You own the design IP but need an independent Gerber set to qualify a backup fabricator.
- Failure analysis support: Recovering the design to perform root-cause analysis on field failures—especially useful when the original designer is unavailable.
- Redesign baseline: Starting a next-gen design from a proven HDI layout rather than a blank schematic accelerates development by 4–8 weeks.
If your project involves IoT device boards or high-frequency RF designs, our team applies domain-specific constraints (antenna keep-outs, RF shielding zones, matched-length routing) during recovery.
Related Board-Type Services
HDI boards often overlap with other specialty categories. Depending on your board’s construction, these related services may apply:
- Multilayer board reverse engineering — for non-HDI boards above 6 layers
- FPC reverse engineering — for flex or rigid-flex HDI assemblies
Can you reverse engineer an HDI board without destroying it?
Partial recovery is possible using X-ray and surface imaging alone, but full HDI PCB reverse engineering requires controlled delamination to capture every microvia and internal trace. We need at least one sacrificial sample. If only one board exists, we discuss risk mitigation—X-ray-heavy workflows can recover 70–85% of the design non-destructively, with targeted delamination of select areas to fill gaps.
What is the minimum trace/space you can recover from an HDI board?
Our current optical and X-ray resolution supports recovery down to 40/40 µm (≈1.6/1.6 mil) trace/space. Below 40 µm—common on substrate-like PCBs (SLP)—we evaluate feasibility case-by-case using SEM imaging. Most commercial HDI boards use 50/50 µm or larger, which is well within our standard capability.
How do you handle impedance-controlled HDI stackups?
We measure dielectric thickness at 5+ points per layer using calibrated cross-sectioning, identify the laminate system (Megtron, IS-series, TU-series, etc.), and reconstruct the impedance model in a 2D field solver. Reported Z₀ accuracy is typically ±3 Ω compared to the original design intent. The impedance report is included in every HDI deliverable package.
Do you support ELIC (every-layer-interconnect) boards?
Yes. ELIC boards are the most complex HDI category because every layer contains microvias with no through-hole core. We’ve recovered ELIC designs up to 20 layers. Turnaround is longer (18–22 working days) and cost is higher due to the additional delamination and imaging steps required. Contact us for a feasibility assessment before shipping.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewWorking on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote