What Is High Density PCB Reverse Engineering?
High density PCB reverse engineering is the process of extracting a complete manufacturing dataset — Gerber files, schematic, BOM, and stackup specification — from an existing HDI (High Density Interconnect) board when original design files are unavailable. HDI boards use microvias (typically 75–150 µm drill), stacked or staggered via structures, 3/3 mil (75/75 µm) or finer trace/space, and often 8–20+ copper layers on thin core/prepreg builds. These features make the reverse engineering process significantly harder than standard multilayer work, demanding specialized imaging, controlled delayering, and careful impedance reconstruction.
Why HDI Boards Are Harder to Reverse Engineer
Not every reverse engineering shop can handle true HDI. The difficulty comes from several compounding factors that don’t exist on conventional boards:
- Microvia stacks: Stacked, staggered, and skip vias connect non-adjacent layers. A 12-layer HDI board can have 4–6 distinct via types, each with different drill diameters (75 µm laser-drilled vs. 200 µm mechanical). Missing even one via connection corrupts the netlist.
- Fine trace/space: At 3/3 mil or 2.5/2.5 mil geometries, standard 1200 DPI scanning can’t resolve adjacent traces. We use 4800+ DPI optical imaging and cross-section microscopy to capture every feature.
- Thin dielectrics: Core thicknesses of 50–100 µm (2–4 mil) mean mechanical delayering must remove material in increments under 25 µm to avoid destroying the next copper layer. Aggressive grinding destroys data permanently.
- Embedded passives & components: Some HDI designs embed capacitors or resistors within inner layers. These are invisible from the surface and only discovered during delayering.
- Impedance sensitivity: HDI boards serving 5G, high-speed serial, or DDR4/DDR5 memory interfaces require impedance-controlled trace reconstruction — not just geometry recovery but dielectric constant and loss tangent matching.
How We Approach High Density PCB Reverse Engineering
Step 1 — Non-Destructive Assessment
Before any material is removed, we photograph both sides at high resolution, X-ray the board to map internal via structures, and catalog every component with manufacturer part numbers. X-ray is critical on HDI: it reveals buried and stacked via columns that surface inspection cannot detect. On a recent 14-layer HDI telecom board, X-ray identified three buried via spans that surface imaging missed entirely.
Step 2 — Component Removal & BOM Generation
All surface-mount components are desoldered and logged. Fine-pitch BGAs (0.4 mm and 0.5 mm pitch) are removed with IR rework stations to avoid pad damage. We cross-reference every part against distributor databases and flag obsolete or custom-marked ICs. The BOM includes manufacturer PN, package, value, tolerance, and suggested alternates for EOL parts.
Step 3 — Layer-by-Layer Imaging
This is where HDI work diverges from standard multilayer board recovery. Each copper layer is exposed by precision surface grinding or chemical etching, then scanned at 4800 DPI minimum. Our engineers verify each layer’s alignment against fiducials before proceeding. On boards with 3/3 mil trace/space, a single misaligned scan can shift hundreds of nets.
Step 4 — Via Mapping & Netlist Extraction
Every via type — through-hole, blind, buried, stacked micro, staggered micro — is cataloged with its span (e.g., L1–L3, L4–L6). The via map is merged with layer images to produce a complete netlist. We run automated DRC against the extracted netlist and then manually verify critical signal paths (differential pairs, power rails, clock trees).
Step 5 — Schematic & Gerber Generation
From the verified netlist and BOM, our engineers reconstruct the schematic in hierarchical blocks. Gerber/ODB++ files are generated with the recovered stackup, drill files for each via type, and impedance notes. The deliverable package includes fabrication notes specifying laminate material (e.g., Megtron 6, IT-180A), copper weights, and finish.
Typical Specifications We Recover
| Parameter | Typical HDI Range | Our Recovery Capability |
|---|---|---|
| Layer count | 8–20+ | Up to 24 layers verified |
| Minimum trace/space | 3/3 mil (75/75 µm) | Down to 2.5/2.5 mil |
| Microvia drill | 75–150 µm laser | 75 µm minimum mapped |
| Via types | Stacked, staggered, skip, through | All types including via-in-pad |
| Board thickness | 0.8–2.0 mm | Full range |
| Impedance targets | 50 Ω single-ended, 85–100 Ω differential | Reconstructed with ±5% tolerance |
| Laminate identification | FR-4 high-speed, Megtron, IS410 | Cross-section + Dk/Df matching |
Cost and Lead Time for HDI Reverse Engineering
HDI boards cost more to reverse engineer than standard multilayer designs because of the additional imaging passes, via mapping complexity, and impedance reconstruction work. Here are realistic ranges:
| Board Complexity | Layer Count | Estimated Cost (USD) | Lead Time (Working Days) |
|---|---|---|---|
| Moderate HDI | 8–10 layers, 1+N+1 buildup | $2,800 – $5,500 | 8–12 |
| Complex HDI | 12–16 layers, 2+N+2 buildup | $5,500 – $12,000 | 12–18 |
| Advanced HDI | 18–24 layers, 3+N+3 or any-layer | $12,000 – $25,000+ | 15–25 |
Pricing depends on board area, component count, number of unique via spans, and whether impedance simulation is required. Boards with high-Tg or specialty laminates may add 10–15% due to the material identification step. We provide a firm quote within 48 hours of receiving your board or high-resolution photos.
Common Failure Points — And How We Avoid Them
Knowing what goes wrong is as important as knowing the process. These are the failure modes we see most often from shops without HDI-specific experience:
- Missed buried vias: If a shop only scans surfaces and through-holes, buried via spans (e.g., L3–L10 on a 14-layer board) are invisible. We X-ray every board before delayering and cross-reference via maps against the netlist.
- Trace bridging at fine pitch: At 3/3 mil, a 0.5 mil scanning error merges adjacent traces into one net. We verify ambiguous areas under 200× microscopy.
- Incorrect stackup reconstruction: Guessing dielectric thickness instead of measuring it produces Gerbers that fail impedance targets on the fabricated clone. We measure every dielectric layer with calibrated cross-sectioning.
- Pad damage during BGA removal: Ripping pads off a 0.4 mm pitch BGA site destroys connectivity data. We use controlled IR profiles specific to each solder alloy.
Which Industries Need HDI Reverse Engineering?
HDI boards appear in nearly every sector pushing miniaturization or high-speed signaling:
- Telecommunications / 5G: Base station boards with 16+ layers, multiple via spans, and strict impedance control.
- Medical devices: Implantable and portable diagnostics using 10-layer HDI on 0.8 mm total thickness.
- Aerospace & defense: Radar and avionics modules — often combined with RF signal path recovery on mixed-material stackups.
- Consumer electronics: Smartphone and wearable main boards with any-layer HDI and embedded components.
- IoT & edge computing: Compact IoT device boards where HDI enables small form factors with dense routing.
Deliverables You Receive
- Gerber RS-274X or ODB++ with separate drill files per via type
- Stackup drawing with measured dielectric thicknesses and identified laminate grades
- Hierarchical schematic (Altium, KiCad, or OrCAD format)
- Complete BOM with manufacturer PNs, alternates, and sourcing notes
- Impedance report with target values and simulated results
- Layer-by-layer high-resolution scan archive
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewFrequently Asked Questions
How many sample boards do you need for high density PCB reverse engineering?
We typically need two identical boards: one for non-destructive X-ray and imaging, and one for destructive delayering. For boards with 16+ layers or any-layer HDI, a third sample is recommended as a backup in case a delayering pass damages a critical layer. Single-sample work is possible on simpler 8–10 layer HDI but increases risk.
Can you reverse engineer HDI boards with embedded components?
Yes. Embedded passives (capacitors, resistors) and embedded copper coin thermal structures are identified during cross-sectioning. We document their placement, values, and layer positions in both the Gerber output and schematic. This adds 2–3 working days to the typical timeline.
What if the board uses any-layer HDI (every layer interconnected by microvias)?
Any-layer HDI is the most complex structure we handle. Every copper layer connects to its neighbors through laser-drilled microvias, meaning there are no conventional through-hole vias at all. We map each via span individually and verify connectivity with automated netlist comparison. Expect lead times at the upper end of our range (18–25 working days) and pricing above $15,000 for 16+ layer any-layer boards.
Do you guarantee the cloned board will pass impedance testing?
We provide impedance simulation data matched to the recovered stackup. When the clone is fabricated using the specified laminate and copper weights, measured impedance typically falls within ±7% of original values. We do not guarantee fab-house process variation, but our Gerber notes include impedance targets and recommended fabricator capabilities so your manufacturer can hit specs.
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