What Does Multilayer PCB Copy Actually Cost?
Multilayer PCB copy cost typically falls between $400 for a straightforward 4-layer board and $8,000+ for a 16-layer HDI design with blind/buried vias and controlled impedance. The final number depends on layer count, via structure, component density, and whether firmware recovery or netlist extraction is included. Below, we break down every variable so you can benchmark a quote before you commit.
Price Ranges by Layer Count
The table below reflects our typical project pricing for multilayer PCB copy work. These are reverse-engineering fees — Gerber extraction, BOM generation, and schematic recovery — not fabrication costs.
| Layer Count | Typical Price Range (USD) | Turnaround (Working Days) | Key Cost Driver |
|---|---|---|---|
| 4-layer | $400 – $1,200 | 5 – 8 | Standard through-hole vias; moderate BOM |
| 6-layer | $800 – $2,500 | 7 – 12 | Inner power/ground splits; impedance matching |
| 8-layer | $1,500 – $4,000 | 10 – 15 | Blind vias, tighter trace/space (≤ 4 mil) |
| 10-layer | $2,500 – $5,500 | 12 – 18 | Mixed via types; high-speed differential pairs |
| 12-layer | $3,500 – $6,500 | 14 – 20 | Sequential lamination; BGA escape routing |
| 14–16-layer | $5,000 – $8,000+ | 18 – 25 | HDI micro-vias; stacked via-in-pad; RF shielding |
These ranges assume one sample board in good physical condition. Damaged boards, corroded pads, or boards with potting compound add 15–30 % to both cost and time. For a complete board cloning cost overview, including fabrication and assembly, see our dedicated guide.
Why Does Layer Count Drive Cost So Hard?
Every additional copper layer requires a separate imaging, etching, and verification cycle during reverse engineering. On a 4-layer board our engineers typically image two internal layers after de-lamination — about two hours of cross-section prep. On a 12-layer board that becomes ten internal layers, each needing alignment registration to within ±1 mil across the panel.
De-lamination and imaging complexity
Inner layers are exposed by chemically or mechanically removing copper and dielectric one layer at a time. Thinner dielectric cores (common in 10+ layer HDI boards using 2-mil prepreg) are more fragile, increasing the risk of trace damage during separation. When a trace is lost, we reconstruct it from netlist inference — possible, but it adds engineering hours.
Via structure multiplier
Through-hole vias are simple to map. Blind vias (connecting an outer layer to one inner layer) and buried vias (connecting two inner layers only) each require separate drilling analysis. A 12-layer board with three sequential lamination stages can contain six distinct via span types. Our engineering cost driver analysis covers this in detail.
Impedance and stackup reconstruction
For boards carrying signals above 100 MHz — DDR3/4 memory buses, PCIe, USB 3.x — we reconstruct the full stackup: dielectric constants, copper weights, and trace geometry needed to hit target impedance (typically 50 Ω single-ended, 90–100 Ω differential). This is not optional on 6+ layer boards with high-speed interfaces; skipping it produces Gerbers that fabricate but fail signal integrity.
Which IPC Class Does Your Multilayer Board Need?
IPC class selection directly affects trace/space tolerances, annular ring minimums, and therefore the cost of both reverse engineering and subsequent fabrication. A Class 2 board (general electronics) tolerates ±2 mil on trace width; Class 3 (high-reliability, military, medical) tightens that to ±1 mil and demands 100 % netlist verification. When we copy a multilayer board, we match the original IPC class — or upgrade it if you need higher reliability on the clone.
PCB assembly
IPC Class Selector, Class 1, 2 or 3
Answer five questions about how the product is used and see which acceptance class fits, and what it changes in your design and your price.
How this is calculated
IPC-A-610 and IPC-6012 define three classes. Class 1 is general electronics where function at delivery is all that is required. Class 2 is dedicated service electronics, where continued performance matters but uninterrupted service is not critical, and it covers most industrial and consumer products. Class 3 is high reliability, where downtime cannot be tolerated and the equipment must work on demand.
The differences are concrete rather than philosophical. Class 3 requires 25 µm of barrel copper against 20 µm for Class 2, and a genuine 0.05 mm external annular ring where Class 2 permits a 90° breakout. Inspection is tighter, sampling plans are stricter, and more of the board gets looked at.
The common mistake is buying Class 3 as a reassurance. It typically adds 15 to 30 % to fabrication cost, and if your design has not been drawn with Class 3 spacing and pad sizes from the start, declaring it late simply produces yield failures at the fabricator. Choose it because the application requires it, then design to it.
Use the selector above to determine which IPC class applies to your application. Class 3 projects typically add 20–35 % to the reverse-engineering fee because every via, pad, and trace must pass tighter inspection criteria per IPC-A-610 and IPC-6012.
Hidden Cost Factors Beyond Layer Count
Layer count is the primary variable, but these secondary factors regularly shift a multilayer PCB copy cost estimate by 20–50 %:
- BGA and fine-pitch components: A board with three 0.4 mm-pitch BGAs requires X-ray imaging to map pad-to-via connections on inner layers. Each BGA adds roughly $150–$300 to imaging costs.
- Embedded passives or copper coin inserts: Non-standard stackup features demand manual CAD reconstruction that automated tools cannot handle.
- Firmware on protected MCUs: If the board has a locked microcontroller whose firmware is needed for a functional clone, firmware extraction fees are separate — typically $300–$2,000 depending on the chip family and protection level.
- Netlist extraction and schematic recovery: Some clients need only Gerbers; others need a full schematic with net names. Schematic recovery adds 30–50 % to the base price. See our netlist extraction cost page for specifics.
- Rush delivery: Compressing a 15-day project into 5 working days is possible for boards up to 8 layers but carries a 50–80 % rush surcharge. Our same-week delivery guide explains what is realistic.
How We Price a Multilayer PCB Copy Project
Our quoting process follows three steps:
- Photo review (free, 24 h): You send top/bottom photos and tell us the layer count (or we estimate it from board thickness and via types). We return a budgetary range.
- Physical inspection (after shipping): We X-ray BGA areas, measure board thickness with a micrometer, and identify via types. This narrows the quote to ±10 %.
- Firm quote and scope lock: We confirm deliverables (Gerber only, Gerber + BOM, Gerber + BOM + schematic), IPC class, and turnaround. Price is fixed from this point.
We never charge per-layer flat rates. A 6-layer board with two BGAs and controlled impedance is more work than an 8-layer board with all through-hole vias and simple digital logic. Flat-rate pricing punishes simple boards and under-estimates complex ones — both are bad for the client. If a quote you receive elsewhere seems surprisingly low, check what cheap PCB copy quotes typically omit.
Common Risks and How They Affect Cost
| Risk | Impact on Cost | Mitigation |
|---|---|---|
| Damaged sample board | +15–30 % | Send a working unit; we return it after imaging |
| Conformal coating / potting | +10–20 % | Chemical removal adds time; some coatings damage silkscreen |
| Obsolete components | BOM cost increase | We flag EOL parts and suggest drop-in replacements |
| Incorrect layer-count assumption | Re-quote required | Send board thickness measurement (caliper) with photos |
| Skipped impedance verification | Functional failure on clone | Always include stackup reconstruction for ≥ 6-layer high-speed boards |
Deliverables You Should Expect
A complete multilayer PCB copy package from our lab includes:
- Gerber RS-274X files (copper, mask, silk, drill) for every layer
- ODB++ or IPC-2581 output on request
- BOM with manufacturer part numbers, package footprints, and reference designators
- Stackup drawing with dielectric thicknesses and copper weights
- Impedance simulation report (for controlled-impedance boards)
- Optional: full schematic in Altium, KiCad, or OrCAD format
All files are delivered digitally; we can also ship the original board back to you at project close.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewFrequently Asked Questions
Is 4-layer PCB copy significantly cheaper than 6-layer?
Yes. A typical 4-layer board with through-hole vias costs $400–$1,200 to reverse-engineer, while a 6-layer board with impedance control starts at $800 and can reach $2,500. The jump comes from additional de-lamination steps and the need for stackup reconstruction on most 6-layer designs.
Can you copy a multilayer board from just photographs?
No. Photos help us estimate layer count and BGA complexity for a budgetary quote, but accurate Gerber extraction requires the physical board. We need to de-laminate inner layers and X-ray BGA pad connections — neither is possible from images alone.
Does multilayer PCB copy cost include fabrication?
Our standard quote covers reverse engineering only: Gerber files, BOM, and optional schematic. Fabrication and assembly are separate. We can recommend vetted fabrication partners or hand off files directly to your preferred fab house.
What if my board has both blind and buried vias?
Mixed via structures are common on 8+ layer HDI boards. Each via span type requires separate analysis during de-lamination. Expect a 20–40 % cost increase compared to a same-layer-count board with only through-hole vias, plus 3–5 additional working days.
How do I reduce multilayer PCB copy cost?
Send a clean, undamaged board. Provide any existing documentation (even partial schematics or old Gerbers). Choose standard turnaround instead of rush. And confirm whether you truly need a full schematic or only Gerber + BOM — dropping the schematic saves 30–50 % of engineering time.
Related Resources
- What drives PCB reverse engineering cost
- Circuit board cloning — full cost and lead time
- Netlist extraction pricing and turnaround
- Rush PCB copy — when same-week delivery works
- Firmware extraction cost and feasibility
- What cheap PCB copy quotes leave out
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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