Lost PCB Schematic Recovery: What Our Engineers Can Actually Rebuild
Yes, a lost PCB schematic can be recovered. Through board-level reverse engineering, our lab extracts a netlist, Gerber fabrication data, and a bill of materials directly from the physical PCB—no original design files required. The recovered schematic is a functional representation accurate enough to manufacture, test, and modify the board. Recovery is realistic for boards from 1 to 16+ layers, though complexity, board condition, and embedded IC protection each affect turnaround and completeness.
Why Schematics Get Lost in the First Place
Most lost-schematic situations we encounter fall into a few predictable buckets. Understanding yours helps set expectations for what the recovery will look like.
- Original designer left the company — files stored on a personal laptop or local drive, never committed to version control.
- EDA tool migration — a decade-old OrCAD or Protel project that no current license can open, and export was never done.
- Acquisition or outsourced design — the IP was supposed to be delivered but the contract didn’t specify source files, only Gerbers or bare boards.
- Fire, flood, or server failure — physical or digital disaster with no off-site backup.
- Legacy product still in production — the board has been manufactured for 15+ years and nobody remembers who designed revision A.
In every case the physical board itself is the last source of truth. As long as one working (or even partially damaged) sample exists, recovery can begin. For context, you don’t need the original schematic to clone a PCB—the board is the documentation.
What Exactly Can Be Recovered?
The word “schematic” means different things to different engineers. Here is a concrete breakdown of every deliverable our lost PCB schematic recovery process can produce, and the realistic accuracy you should expect.
| Deliverable | What It Contains | Typical Accuracy | Format |
|---|---|---|---|
| Gerber files (RS-274X) | Copper layers, solder mask, silkscreen, drill file | ±0.5 mil trace/space on standard boards | .gbr, .drl |
| Netlist | Every electrical connection, node by node | 99%+ after continuity verification | IPC-D-356, Altium, KiCad |
| Bill of Materials (BOM) | Reference designators, values, packages, manufacturer P/N where identifiable | 90–98% depending on marking legibility | .xlsx, .csv |
| Schematic diagram | Hierarchical or flat schematic with net names, component values, power rails | Functional equivalent of original | .SchDoc, .kicad_sch, PDF |
| PCB layout (board file) | Component placement, routing, stackup, impedance-controlled nets flagged | Matches physical board within ±1 mil | .PcbDoc, .kicad_pcb |
| Firmware image | Binary dump from MCU/FPGA (if chip allows readout) | Bit-exact when unprotected; varies with lock bits | .hex, .bin |
The schematic diagram is the deliverable most people think of, but the netlist is the engineering backbone. A netlist verified against the physical board by automated continuity testing is what guarantees the recovered schematic is electrically correct—not just a pretty drawing.
How Lost PCB Schematic Recovery Works Step by Step
1. Board intake and imaging
We photograph the board at 1200+ DPI on both sides, then catalog every component. On multilayer boards (4, 6, 8, or more layers), X-ray imaging or controlled delamination exposes inner copper. A 4-layer board typically needs two internal images; a 12-layer HDI board may require ten or more passes.
2. Layer extraction and vectorization
Each copper image is converted into vector artwork—polygons, traces, pads—using a combination of automated edge detection and manual cleanup. Trace widths are measured to 0.5 mil resolution. Via drill sizes are captured from the X-ray or physical cross-section.
3. Component identification and BOM build
Every part is identified by package, marking code, and (where possible) manufacturer part number. Unmarked passives are measured in-circuit or with an LCR meter after desoldering. QFN and BGA packages with no visible markings require decapsulation or cross-referencing pin count and pad pitch against known databases.
4. Netlist extraction
Pad-to-pad connections are traced across all layers. The resulting netlist is verified with a flying-probe or fixture test against the physical board. Any discrepancy is investigated trace by trace. This step catches ~98% of errors before the schematic is even drawn.
5. Schematic capture
Using the verified netlist, our engineers draw a hierarchical schematic organized by functional block: power supply, digital core, analog front-end, I/O connectors. Net names are assigned logically (VCC_3V3, SPI_CLK, etc.) rather than left as anonymous node numbers. The result is a schematic you can hand to a new engineer and have them understand the circuit—not just a netlist dump with symbols.
6. Design rule check and output
Gerber files are generated, DRC is run against IPC-2221 / IPC-2222 rules for the relevant board class, and the full package is delivered. Turnaround ranges from 5 working days for a simple 2-layer board to 20–30 days for a dense 10+ layer design.
What Cannot Be Recovered
Honesty matters more than a sales pitch. Here are the realistic limits of lost PCB schematic recovery:
- Design intent annotations — comments like “R7 sets gain to 2.5×” or “C12 critical for EMI” exist only in the designer’s head. We recover the circuit, not the reasoning.
- Firmware from locked MCUs — if a microcontroller’s read-protection fuse is set (e.g., STM32 RDP Level 2, PIC CRP3), the binary may be unrecoverable without invasive techniques. Our firmware recovery process covers what is feasible per chip family.
- FPGA bitstreams with encryption — Xilinx and Intel FPGA bitstream encryption (AES-256) is currently unbreakable in a practical sense.
- Impedance targets without a stackup spec — we can measure trace geometry and estimate impedance, but the original target (e.g., 50 Ω ±10%) is an assumption unless the board’s function makes it obvious (USB, DDR, RF).
- Severely destroyed boards — if more than ~40% of the copper area is missing or corroded beyond imaging, gaps in the netlist are unavoidable. Even so, a damaged board can often still be partially copied with engineering interpolation filling known circuit topologies.
How Accurate Is a Recovered Schematic Compared to the Original?
The recovered schematic is an electrical equivalent, not a cosmetic clone. Net names, sheet organization, and symbol choices will differ from whatever the original designer used. But every connection, every component value, and every pin assignment will match the physical board. For manufacturing purposes the recovered files are drop-in replacements: you can send the Gerbers to any fab house and the BOM to any assembler.
Where the original schematic used proprietary symbols or hierarchical blocks, our version will use standard library parts. This is actually an advantage—it means the recovered schematic is portable across EDA tools without dependency on a custom library nobody else has.
When Should You Recover a Schematic vs. Redesign?
Recovery is faster and cheaper when the existing board works and you need to continue producing it, repair it, or make minor modifications. Redesign makes sense when the board is fundamentally obsolete or you want to change its architecture. For a detailed comparison, see our guide on when to reverse-engineer versus redesign.
| Factor | Recover Schematic | Redesign |
|---|---|---|
| Board still works and meets spec | ✔ Best choice | Unnecessary cost |
| Need to change >30% of BOM | Recover first, then modify | ✔ May be more efficient |
| Original components obsolete | Recover + cross-reference | ✔ If architecture change needed |
| Timeline <2 weeks | ✔ Feasible for ≤6 layers | Unlikely |
| No working sample exists | Limited (need at least partial board) | ✔ Only option |
What to Send Us for a Lost PCB Schematic Recovery Quote
To scope the project accurately, we need:
- One working sample (preferred) or a non-working sample with known failure mode.
- Layer count if known, or board thickness (helps estimate).
- Any partial documentation — even a hand-drawn block diagram, an old BOM, or a photo of the silkscreen side speeds things up.
- Target deliverables — Gerber only? Full schematic? Firmware dump?
Check our sample condition and quantity guidelines before packing. If you already have Gerber files but need a schematic back-annotated from them, that is a related but different workflow—see recovering a schematic from Gerber data.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewFrequently Asked Questions
How long does lost PCB schematic recovery take?
A 2-layer board with fewer than 100 components typically takes 5–7 working days. A 6-layer board with BGA packages and 500+ components averages 12–18 working days. Boards above 10 layers or with potting/conformal coating add 5–10 days for preparation alone.
Can you recover a schematic if the board is partially burned or corroded?
Usually yes, with caveats. If the damaged area is less than ~40% of the board, we can reconstruct missing nets by analyzing symmetry, known IC pinouts, and standard circuit topologies. Beyond that threshold, gaps in the netlist become unavoidable and we flag them clearly in the deliverables.
Is the recovered schematic good enough for certification (UL, CE)?
The recovered files are electrically equivalent to the original and suitable for manufacturing. However, certification bodies may require additional documentation (test reports, safety analysis) that goes beyond what reverse engineering alone provides. We deliver the engineering files; your compliance team handles the regulatory submission.
Do I need to send the physical board, or can you work from photos?
We need the physical board. Photos cannot capture inner-layer copper, via structures, or component values with the precision required. High-resolution photos can supplement but never replace a physical sample.
What if some components are missing from the board?
Missing components are identified by their pad footprint, silkscreen marking, and surrounding circuit context. In many cases we can determine the correct part number. Where we cannot, we document the footprint and likely value range so you can verify with testing.
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote