What Is ODB++ Generation?
ODB++ generation is the process of compiling all board fabrication and assembly data—copper layers, drill files, netlist, component placement, and BOM—into a single hierarchical database that a manufacturer can import without juggling dozens of loose files. When we generate ODB++ from a reverse-engineered board, the output is a self-contained directory structure (typically delivered as a .tgz archive) that carries every piece of information a fab house and assembler need to reproduce the board.
Unlike a Gerber package where each layer is an independent file with no inherent relationship to the others, ODB++ embeds net connectivity, layer stackup definitions, and component attributes in one structured tree. That distinction matters most on complex boards—10+ layers, blind/buried vias, mixed SMD and through-hole—where a mismatched file set can silently produce scrap.
Where ODB++ Generation Sits in the Reverse Engineering Process
ODB++ is a late-stage deliverable. It comes after physical capture, layer extraction, netlist verification, and DRC. Here is the typical sequence our engineers follow inside a PCB reverse engineering services project:
- Physical capture – High-resolution optical scanning of each copper layer, plus non-destructive X-ray inspection for hidden vias and BGA pad connections.
- Layer-by-layer redraw – Traces, pads, and planes are redrawn in EDA software (Altium, Cadence Allegro, or Mentor PADS) at 1:1 scale. Typical trace/space accuracy target: ±0.5 mil (0.0127 mm).
- Netlist extraction and DRC – Connectivity is verified against the physical board. Open/short violations are resolved before any output is generated.
- Drill data compilation – All through, blind, buried, and micro-via holes are tabulated with tool sizes, plating types, and span definitions. This stage overlaps with drill file generation from the physical board.
- BOM and placement – Component reference designators, values, package footprints, and X/Y/rotation data are captured.
- ODB++ export – The EDA design is exported to ODB++ format. The engineer then validates the archive against the original design database to catch export artifacts.
Steps 1–5 take the bulk of the project time. The ODB++ export itself is fast—minutes, not days—but the validation afterward adds 2–4 hours on a 12-layer board because every net, drill span, and component attribute must be cross-checked.
What’s Actually Inside an ODB++ Package?
An ODB++ archive is a directory tree, not a flat file. Understanding its structure helps you verify what you receive.
| Directory / File | Contents | Why It Matters |
|---|---|---|
| steps/pcb/layers/ | One sub-folder per copper, solder-mask, silkscreen, and paste layer | Each layer carries features (pads, traces, fills) with net assignments—not just geometry |
| steps/pcb/netlists/ | Full netlist with net names and pin-to-net mapping | Enables the fab to run their own DRC and impedance checks |
| steps/pcb/eda/ | Component attributes, BOM data, pick-and-place coordinates | Assembly house can pull placement and BOM from the same archive |
| matrix/ | Layer stackup order, types (signal, plane, mixed), polarity | Defines build sequence; eliminates the “which layer is which?” problem |
| misc/ | Drill tool definitions, slot routes, board outline | Consolidates all mechanical data in one place |
| fonts/ | Font definitions for silkscreen text rendering | Prevents character substitution on legend layers |
A well-formed ODB++ archive for a 10-layer board with 800 components typically runs 15–40 MB uncompressed. If the archive you receive is under 1 MB, something is missing—usually the netlist or the component attribute data.
How Does ODB++ Generation Differ From Gerber Output?
Both formats describe the same physical board, but they organize data differently. Choosing between them depends on your manufacturer’s import capability and your downstream workflow. For a deeper comparison, see our guide to Gerber, ODB++, and IPC-2581 differences.
| Attribute | Gerber (RS-274X / X2) | ODB++ |
|---|---|---|
| File structure | Separate file per layer + drill files + readme | Single directory tree / .tgz archive |
| Net information | Gerber X2 embeds limited net attributes; classic RS-274X has none | Full netlist with pin-level mapping |
| BOM / placement | Requires separate CSV/Excel + centroid file | Embedded in /eda/ directory |
| Stackup definition | External document or IPC-2581 supplement | Defined in the matrix file |
| Fab adoption | Near-universal | ~65–70% of advanced fabs; less common at budget shops |
| Risk of mismatch | Higher—files can be mixed from different revisions | Lower—single-source archive |
Our default deliverable set includes both Gerber and ODB++ at no extra cost. If your fab only accepts Gerber, you lose nothing. If they accept ODB++, you gain netlist-aware DFM checks on their side.
Common Failure Points in ODB++ Generation
Generating ODB++ from a reverse-engineered board is not the same as exporting from the original designer’s project file. Several issues are specific to recovery scenarios:
- Missing net names. When a board is reverse-engineered, nets are initially unnamed. Our engineers assign functional names (VCC_3V3, GND, UART_TX) during schematic recovery, but if the project skips schematic-level work, nets export as NET_0001 through NET_nnnn. The ODB++ is technically valid, but harder for the fab to interpret.
- Blind/buried via span errors. If the original stackup isn’t known and must be inferred from cross-sectioning, via spans can be mis-assigned. A via tagged as L1–L4 when it actually spans L1–L6 will cause the fab’s CAM tool to reject the job. We cross-check every via span against X-ray and micro-section data.
- Component attribute gaps. Reverse-engineered BOMs sometimes carry partial manufacturer part numbers—especially on boards with remarked or obscured SMD markings. These gaps propagate into the ODB++ /eda/ data. We flag incomplete entries so the assembler knows which lines need sourcing confirmation.
- Negative-plane polarity. Inner ground and power planes are often stored as negative images. If the ODB++ matrix file marks a negative layer as positive, the fab will etch the inverse. This is a one-checkbox error that causes 100% scrap.
- Export tool version drift. Altium Designer 23.x and 24.x produce slightly different ODB++ structures. Some older CAM tools choke on newer archive versions. We validate every export against at least two independent ODB++ viewers (Valor and Camtastic) before delivery.
When Should You Request ODB++ Instead of Gerber?
ODB++ generation adds the most value in these scenarios:
- Boards with ≥8 layers where drill span management and layer assignment errors become costly.
- Designs going to DFM-aware fabs that run Valor or similar tools—ODB++ lets them catch net-level issues before tooling.
- Combined fab + assembly orders where a single archive eliminates the risk of BOM/placement file version mismatch.
- Archival / long-term IP documentation where you want one file that fully describes the board five years from now.
For simple 2–4 layer boards going to a budget fab, Gerber is usually sufficient and more universally accepted.
Our ODB++ Generation Workflow: Specifics
After the EDA design passes DRC, the engineer runs ODB++ export with these settings locked:
- Layer mapping verified against the matrix—signal, plane, mixed, drill, mask, paste, silk all tagged correctly.
- Net export enabled with hierarchical net names (not flattened).
- Component data export includes: RefDes, package, value, MPN (where known), X/Y in mm, rotation in degrees, top/bottom side flag.
- Drill export uses plated/non-plated separation with tool tolerances noted (typically ±0.05 mm for PTH, ±0.025 mm for micro-vias).
- Archive is compressed to .tgz and opened in an independent viewer for a layer-by-layer visual audit.
Turnaround for the ODB++ export and validation step alone is typically same-day once the underlying design is complete. The full project—from physical board to delivered ODB++ archive—ranges from 5 working days for a 4-layer board to 15–25 working days for a 14+ layer HDI design. If you need a board redraw and layout recovery, ODB++ generation is included in the deliverable package.
Validating the ODB++ You Receive
Quick Checks You Can Do Yourself
- Unpack the .tgz and confirm the /steps/pcb/layers/ folder has the correct number of copper layers.
- Open the matrix file and verify layer order matches your known or expected stackup.
- Check that /steps/pcb/netlists/ is not empty—an empty netlist directory means net data was not exported.
- Confirm the /eda/ directory lists components with non-zero X/Y coordinates.
Advanced Validation
Load the archive into a free ODB++ viewer (Mentor’s Valor Free Viewer or the Ucamco Reference Viewer) and run a basic connectivity check. Any net flagged as open or shorted should be reported back before you send files to the fab.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewCan every PCB manufacturer accept ODB++ files?
No. Roughly 65–70% of mid-to-high-tier fabricators support ODB++ import. Budget prototype houses in Asia often only accept Gerber + Excellon drill. We deliver both formats by default so you are covered regardless of your fab’s capability.
Is ODB++ generation possible if I only have Gerber files, not the original EDA project?
Not directly. ODB++ requires net and component data that plain Gerber RS-274X files don’t carry. We would need to import your Gerbers into an EDA tool, reconstruct the netlist, and then export ODB++. This is essentially a full reverse engineering workflow starting from files rather than a physical board.
Does ODB++ include pick-and-place data for SMT assembly?
Yes. The /eda/ directory contains component X/Y coordinates, rotation, and side (top/bottom) in a structured format. Many assemblers can import this directly, eliminating the need for a separate centroid file. For details on how placement data integrates with assembly, see our page on pick-and-place file generation.
What is the typical file size of an ODB++ archive?
For a 10-layer board with ~800 components, expect 15–40 MB uncompressed (3–8 MB as .tgz). Extremely dense HDI boards with 2,000+ components and 16 layers can reach 80–100 MB uncompressed. If your archive is suspiciously small, check for missing layers or an empty netlist directory.
How does ODB++ handle blind and buried vias?
Each drill tool in ODB++ carries a span definition (e.g., L1–L2 for a micro-via, L3–L10 for a buried via). The matrix file defines layer order, so the fab’s CAM software can validate that via spans are physically possible for the stated stackup. This is one area where ODB++ is significantly more robust than Gerber, which requires a separate drill file per span with manual documentation.
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote