What Determines PCB Copy Lead Time?
A typical PCB copy lead time ranges from 3 working days for a simple 2-layer board with no programmed ICs to 3–4 weeks for a 10+ layer design that includes firmware recovery, impedance-controlled stackups, and hard-to-source components. The spread is not marketing fluff — it reflects real engineering steps that cannot be parallelized. Understanding which phases apply to your board lets you predict your actual delivery window before you commit a dollar.
The Five Phases That Build Your PCB Copy Lead Time
Every PCB copy project passes through a defined sequence. Some phases overlap; others are strict gates. Here is what our engineers actually work through, with realistic hour and day ranges.
| Phase | What Happens | Simple Board (2–4 layers) | Complex Board (8–16 layers) |
|---|---|---|---|
| 1. Board Analysis & Photography | High-res imaging of every layer, X-ray for buried vias, component cataloging | 2–4 hours | 1–2 days |
| 2. Schematic & Gerber Extraction | Netlist capture, trace routing in CAD, DRC checks | 1–2 days | 5–10 days |
| 3. IC / Firmware Recovery | MCU readout, CPLD/FPGA bitstream extraction (authorized only) | 0 days (no programmed ICs) | 2–7 days |
| 4. BOM Sourcing & Cross-referencing | Identify every passive/active, find in-stock or cross-reference obsolete parts | 0.5–1 day | 2–5 days |
| 5. Prototype Fabrication & Assembly | PCB fab, SMT assembly, programming, functional test | 2–3 days (domestic quick-turn) | 5–10 days |
Add the columns and you see: a clean 2-layer board lands at roughly 3–5 working days. A dense 12-layer industrial controller with two locked MCUs and three obsolete ICs can stretch to 18–25 working days. Neither number is padded — they reflect actual bench time our team logs.
Why Layer Count Moves the Needle Most
Layer count is the single largest time driver in the Gerber-extraction phase. Each additional copper layer requires separate imaging, registration alignment, and net verification. A 4-layer board typically doubles the extraction time compared to a 2-layer. Beyond 8 layers, blind and buried vias force X-ray micro-sectioning, adding another day per via type.
Impedance-controlled stackups (common in RF, high-speed digital, and automotive boards) also add time because the engineer must measure dielectric thickness, calculate trace geometry, and verify characteristic impedance — typically 50 Ω single-ended or 90/100 Ω differential — before releasing Gerbers. Skip this step and your clone may pass visual inspection but fail signal integrity at speed.
IC Recovery: The Hidden Schedule Risk
If your board carries a microcontroller with read protection enabled, firmware recovery becomes a gating task. A straightforward readout on an unprotected PIC or STM8 takes hours. A locked STM32 with RDP Level 2, or a security-fused CPLD, may require days of lab work — or may not be feasible at all.
Our policy: we perform IC recovery only on devices you own or are authorized to duplicate. Proof of ownership or a signed authorization letter is required before we begin. For details on how we handle IP protection, see our rush PCB copy turnaround guide which also covers expedited firmware timelines.
When multiple ICs on one board need recovery, the tasks usually run in parallel — but if one chip proves resistant, it can stall the entire project. We flag this risk during feasibility review, typically within 48 hours of receiving your board.
BOM Sourcing: Where Calendar Time Hides
Engineering time is predictable. Supply-chain time is not. A single obsolete ASIC or discontinued connector can add 1–3 weeks to your PCB copy lead time while we source from secondary markets or qualify a cross-reference.
Common BOM delay triggers:
- End-of-life power management ICs (especially older TI/ON Semi parts)
- Proprietary connectors with long factory lead times (Hirose, JAE narrow-pitch)
- Ceramic capacitors in specific voltage/package combos still affected by allocation cycles
- Custom-wound inductors or transformers that must be replicated from scratch
We mitigate this by starting BOM sourcing in parallel with schematic extraction — not after it. If a part looks risky, we propose a cross-reference early so you can approve or reject the substitution before it becomes a bottleneck. Understanding what actually drives reverse engineering cost helps you anticipate which components will need extra attention.
How to Shorten Your PCB Copy Lead Time
1. Supply Complete Documentation Up Front
If you have any existing schematics, partial BOMs, or even a service manual, send them. Partial data cuts our analysis phase by 20–40%, even if the files are outdated.
2. Ship More Than One Sample Board
We may need to de-solder components for identification or cross-section the PCB for layer verification. A second board lets us keep one intact as a functional reference, avoiding rework loops that add days.
3. Pre-Approve BOM Substitutions
Give us a substitution policy before we start: “equivalent or better specs OK for passives, exact match required for ICs.” This eliminates approval round-trips on every resistor value.
4. Choose Domestic Quick-Turn Fab
Standard offshore PCB fabrication runs 7–10 calendar days plus shipping. Domestic quick-turn (US, EU) can deliver bare boards in 24–72 hours at a premium. On a rush project, this single choice can compress the overall schedule by a full week.
5. Request a Feasibility Review First
Before committing to a full copy, ask for a feasibility assessment. We examine the board, flag locked ICs, identify obsolete parts, and return a realistic timeline within 2 business days — often for no charge on straightforward boards.
PCB Copy Lead Time vs. Cost: The Trade-Off Table
Faster turnaround costs more. Here is a realistic mapping so you can budget both time and money. For a deeper look at the financial side, check our breakdown of factors that move your PCB copy quote.
| Turnaround Tier | Typical Calendar Days | Cost Premium vs. Standard | Best For |
|---|---|---|---|
| Rush / Emergency | 3–5 | +50–100% | Production-down, single simple board |
| Expedited | 7–10 | +20–40% | Mid-complexity boards, tight project deadlines |
| Standard | 12–18 | Baseline | Most projects, best cost-to-quality balance |
| Economy / Batch | 20–28 | −10–20% | Non-urgent, multiple boards, offshore fab |
Be cautious with vendors quoting rock-bottom prices and impossibly short timelines simultaneously. A suspiciously low PCB copy price often means corners are being cut — no impedance verification, no functional test, or firmware simply skipped.
What Can Go Wrong (and How It Extends Lead Time)
Experienced buyers plan for setbacks. Here are the failure modes we see most often:
- Corroded or damaged sample board: Traces under corrosion may be unreadable, requiring destructive cross-sectioning. Adds 1–3 days.
- Unlabeled custom ASICs: If a chip has no markings, we must reverse-engineer its function from the circuit context. Adds 2–5 days and may require a second sample.
- Multi-board systems: Boards that communicate over proprietary protocols need the full set analyzed together. Each additional board adds roughly 60–80% of a single-board timeline.
- Regulatory compliance needs: If you need the clone to pass UL, CE, or FCC, add time for layout adjustments to meet spacing/creepage rules — typically 1–2 days of design review.
Realistic Timeline Examples
Example A: 2-Layer LED Driver, No ICs
Board analysis: 3 hours. Gerber extraction: 1 day. BOM: 4 hours (all standard jellybean parts). Quick-turn fab + assembly: 2 days. Total: 3 working days.
Example B: 8-Layer Industrial Controller, 1 Locked STM32
Board analysis: 1 day. Gerber extraction: 6 days. IC recovery: 3 days (parallel). BOM sourcing: 4 days (one obsolete relay). Fab + assembly: 5 days. Total: 15 working days.
Example C: 14-Layer Telecom Board, 3 FPGAs, Impedance-Controlled
Board analysis: 2 days. Gerber extraction: 10 days. FPGA bitstream recovery: 5 days (parallel, authorized). BOM sourcing: 7 days (multiple long-lead passives). Fab + assembly: 8 days. Total: 22 working days.
How long does a basic PCB copy take?
A straightforward 2-layer board with standard through-hole and SMD components, no programmed ICs, and all parts in stock typically ships in 3–5 working days. This assumes you provide a clean, undamaged sample and approve the BOM without revision cycles.
Can I get a PCB copy in under 24 hours?
Not realistically for a complete copy (Gerber + BOM + assembled board). A bare Gerber file for a very simple 1–2 layer board might be extracted in a single working day, but fabrication and assembly add at minimum another 24–48 hours even on the fastest quick-turn services.
What adds the most time to a PCB copy project?
Three factors dominate: high layer counts (8+ layers), locked microcontrollers requiring firmware recovery, and obsolete components that must be sourced from secondary markets. Any one of these can add a full week to your timeline.
Does firmware recovery delay the whole project?
Not always. We start IC recovery in parallel with Gerber extraction. However, if a chip proves to have stronger-than-expected protection, it can become the critical path. We identify this risk during feasibility review, usually within 48 hours of receiving your board.
How does PCB copy lead time affect total cost?
Rush turnaround (3–5 days) typically carries a 50–100% premium over standard scheduling. The premium covers overtime engineering hours and expedited PCB fabrication. Choosing standard timing (12–18 days) gives the best balance of cost and quality. See our PCB copy cost guide for a full factor breakdown.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
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