A PCB copy quality guarantee means every copied board must function identically to the original — same netlist, same impedance targets, same mechanical fit. Our guarantee is built on five verification stages, IPC-class tolerances documented in writing, and a free-respin commitment if any deliverable fails to match the source board. Below is exactly what that covers, how we enforce it, and where the realistic limits are.
Why a Quality Guarantee Matters for PCB Copying
Reverse-engineering a circuit board is not photocopying. A six-layer FR-4 board with 4/4 mil trace/space, blind vias, and impedance-controlled differential pairs can have over 3,000 nets. One missed via, one swapped pin on a BGA footprint, or one wrong annular ring dimension turns a “copy” into scrap. Without a structured guarantee, you have no contractual recourse when boards arrive from the fab and fail functional test.
Most shops promise “high quality” but never define it. We publish measurable criteria — trace width tolerance of ±0.5 mil on the Gerber, netlist match rate of 100 %, BOM component value accuracy verified against markings and datasheets — so you can audit the deliverable before it ever reaches a fabricator.
What Our PCB Copy Quality Guarantee Covers
| Guarantee Element | Specification | Verification Method |
|---|---|---|
| Netlist accuracy | 100 % match to original board | Automated DRC + manual spot-check of 20 % of nets |
| Trace/space fidelity | ±0.5 mil (±0.013 mm) from measured original | Optical comparator overlay at 50× magnification |
| Layer registration | ≤2 mil (0.05 mm) offset layer-to-layer | Cross-section microsection on prototype run |
| Impedance targets | ±10 % of calculated Z₀ (or tighter if specified) | Stackup simulation in Polar Si9000; TDR on prototype coupon |
| BOM accuracy | Every component value, package, and manufacturer PN verified | Visual marking decode + LCR meter spot-check |
| Mechanical outline | ±0.1 mm board dimensions, ±0.05 mm hole placement | CNC drill file vs. CMM measurement of original |
| Schematic correctness | Schematic back-annotates to Gerber with zero errors | ERC in Altium/KiCad; cross-reference to netlist |
If any element above fails after you receive deliverables, we respin the affected files at no charge. If the respin still does not resolve the issue, we refund the project fee for that deliverable. This is written into every project contract.
Five Verification Stages Behind the Guarantee
Promises without process are marketing. Here is the actual sequence our engineers follow on every project — whether it is a two-layer single-sided remote control board or a 14-layer HDI industrial controller. You can review the full PCB copy workflow from scan to build for process context.
Stage 1 — Incoming Board Inspection
We photograph every surface at 20 MP resolution, measure board thickness with a digital micrometer (±0.01 mm), and log component condition. Damaged pads, corroded traces, or missing components are documented and flagged before work begins. If the sample condition limits achievable accuracy, we tell you upfront — see our board sample condition and quantity guidelines for what makes an ideal sample.
Stage 2 — Layer Imaging and Delayering
Outer layers are scanned optically. Inner layers are exposed through controlled chemical or mechanical delayering, then imaged. Each layer image is aligned to fiducials and converted to vector data. Our tolerance target at this stage is ±0.25 mil positional accuracy on pad centers.
Stage 3 — Netlist Extraction and Cross-Check
We extract the netlist from the captured Gerber data and independently extract a netlist by probing the physical board with a flying-probe fixture. The two netlists are compared node-by-node. Any discrepancy triggers manual re-trace of the affected net. This dual-path method catches errors that purely optical capture misses — especially on inner-layer connections obscured by via fill or solder mask bleed.
Stage 4 — Schematic and BOM Review
The schematic is drawn from the verified netlist, grouped into functional blocks (power, digital, analog, I/O), and reviewed by a second engineer who did not perform the capture. BOM entries are verified against component markings, datasheets, and — where markings are illegible — LCR meter measurements. You do not need to supply the original schematic; we reconstruct it from the board.
Stage 5 — Design Rule Check and Deliverable Package
Final Gerber, drill, and pick-and-place files run through a full DRC against the target fab’s capabilities (minimum annular ring, solder-mask clearance, copper-to-edge). The deliverable package includes: Gerber RS-274X or Gerber X2, Excellon drill files, BOM in Excel, schematic PDF, and — when contracted — native Altium or KiCad project files. Every file set ships with a verification report summarizing the checks above.
What Can Go Wrong — and the Honest Limits
No guarantee is unlimited. Transparency about edge cases is part of our quality commitment.
- Encrypted or protected firmware: If the board contains a microcontroller with read-protection fuses, we can copy the PCB and BOM but cannot guarantee firmware recovery. We will assess feasibility before quoting.
- Severely damaged samples: Boards with burned-through traces, delaminated layers, or missing sections reduce accuracy. We document limitations in the inspection report and adjust the guarantee scope accordingly.
- Proprietary or custom ASICs: If a component is a house-marked or custom die with no public datasheet, we can capture its footprint and pin connections but cannot guarantee a drop-in replacement sourcing path.
- Impedance on flex or exotic substrates: Rogers, polyimide flex, and ceramic substrates require material-specific Dk/Df values. If the original stackup is unknown and the substrate is non-standard, impedance accuracy may widen to ±15 %.
Avoiding mistakes that commonly slow PCB copy projects — like sending a populated board with no reference designators visible — also helps us hit tighter tolerances faster.
How Our Guarantee Compares to Typical Alternatives
| Quality Factor | Generic Copy Shop | Our Guarantee |
|---|---|---|
| Netlist verification | Visual only | Dual-path: optical capture + flying-probe cross-check |
| Impedance control | Not addressed | Stackup simulation + optional TDR coupon |
| BOM accuracy | “Best effort” | Marking decode + LCR meter + datasheet cross-ref |
| Respin policy | Paid revision | Free respin if deliverable fails spec |
| Turnaround transparency | Vague estimate | Milestone schedule with inspection, capture, verify, deliver dates |
| IPC class reference | Not stated | IPC-2221B Class II default; Class III on request |
IPC Standards We Reference
Our quality baseline maps to IPC-2221B (Generic Standard on Printed Board Design) and IPC-A-600 (Acceptability of Printed Boards) Class II for commercial electronics. For medical, aerospace, or military boards, we work to Class III tolerances — tighter annular rings, stricter plating thickness, and 100 % net verification instead of 20 % spot-check on the manual pass. If your board serves a mission-critical application, flag it at quote time so we scope the project correctly.
What You Receive as Proof of Quality
- Verification report (PDF): Layer-by-layer overlay images, netlist comparison log, DRC summary, BOM cross-reference table.
- Gerber preview renders: 3D render of each layer so you can visually confirm layout before fabrication.
- Impedance simulation report: Polar Si9000 output showing target vs. achieved Z₀ for controlled nets.
- Revision history: If any changes were made during review, they are logged with rationale.
These documents give your fabricator — or your own engineering team — full traceability from original board to copied file set.
Getting Started With a Guaranteed PCB Copy
The fastest path is to send your board sample with a brief description of the project goal (clone for production, legacy recovery, second-source qualification). Review our guide to shipping a PCB sample safely for packing and customs tips. We return a feasibility assessment within two business days of receiving the board, including a written scope of guarantee for your specific project.
If you are still evaluating whether copying or redesigning makes more sense, our overview of when to reverse-engineer versus redesign breaks down the decision by cost, timeline, and risk.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewWhat does “100 % netlist match” actually mean?
It means every electrical connection on the copied Gerber files corresponds one-to-one with the connections on the original board. We verify this by extracting a netlist from the Gerber data and independently probing the physical board. The two netlists are compared node-by-node using automated software, and any mismatch is resolved before delivery.
Do you guarantee the copied board will pass my functional test?
We guarantee the files are an accurate electrical and mechanical representation of the original board. If the original board passes your functional test and our files are fabricated to spec, the copy should perform identically. We cannot guarantee against fab-house manufacturing defects, but our DRC and impedance simulation minimize that risk. If a file error causes a functional failure, we respin at no cost.
Is the quality guarantee valid for high-layer-count or HDI boards?
Yes. We apply the same five-stage verification to boards from 1 to 20+ layers, including HDI designs with microvias, stacked vias, and sequential lamination. Tolerances on inner-layer registration tighten for HDI (≤1.5 mil), and we adjust our delayering and imaging process accordingly. The guarantee terms are documented per-project based on actual board complexity.
What if my board sample is partially damaged?
We document the damage during incoming inspection and tell you which areas may have reduced accuracy. For minor damage (a few corroded pads, one missing component), we can typically reconstruct the affected nets from surrounding circuit context. For severe damage (burned-through layers, large missing sections), we narrow the guarantee scope to the recoverable portion and quote accordingly.
How long does the quality-verified PCB copy process take?
A standard 2–4 layer board with moderate complexity ships verified files in 5–8 working days. Boards with 8+ layers, BGAs, or impedance-controlled nets typically take 10–15 working days. Rush service (3–5 days for simple boards) is available. Every quote includes a milestone schedule so you know when each verification stage completes.
Related Pages
- PCB copy and cloning services overview
- Copying a 4-layer board — process and considerations
- Recovering files from obsolete, unsupported boards
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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